Welcome to the 558/658 Course Home
Page for Fall 2006! This serves as the syllabus for the course. The URL
is: http://www.ecs.umass.edu/ece/vspgroup/burleson/courses/558/
Instructor: Wayne Burleson, Professor,
Department of Electrical and Computer Engineering, Tel: 413-545-2382, email:
burleson@ecs.umass.edu, Office: KEB309C, Office Hours: Mon
TA: Basab Datta, e-mail: bdatta@ecs.umass.edu
VLSI TA web-site (Information available about homeworks, labs,
tools and other things that you can't think of!)
The course will cover basic theory and
techniques of digital VLSI design in CMOS technology. Topics include: CMOS
devices and circuits, fabrication processes, static and dynamic logic
structures, chip layout, simulation and testing, low power techniques, design
tools and methodologies, VLSI architecture. We use full-custom techniques to
design basic cells and regular structures such as data-path and memory. There
is an emphasis on modern design issues in interconnect and clocking. We will
also use several case-studies to explore recent real-world VLSI designs (e.g.
Pentium, Alpha, PowerPC StrongARM, etc.) and papers from the recent research
literature. On-campus students will design small test circuits using various
CAD tools. Circuits will be verified and analyzed for performance with various
simulators. Some final project designs will be fabricated and returned to
students the following semester for testing. (4 credits)
Prerequisites: A basic knowledge of digital logic design
(e.g. ECE 112), RLC circuits (eg. ECE 221) and MOS circuits (eg. ECE 323).
On-campus Grading: Homework (20%), Labs (40%), Two midterm exams
(20% ), and a final exam (20%).
Off-campus Grading: Homework (30%), Two midterm exams (40% ), and
a final exam (30%).
Honesty Policy: Consultation with fellow students is
encouraged, especially on design issues. However, directly copying another
student's work defeats the purpose of the assignments and is an honor code
violation. In addition, any collaborations or use of materials from previous
courses, texts, solution manuals or advice from others should be clearly stated
in the homework or lab report. Give credit where credit is due! Be honest about
your own abilities and accomplishments!
For 658 students: If you are a grad student, (either on-campus
or off-campus) you should take 658. You can not take both 558 and 658. For 658,
there will be additional readings and additional or alternate problems on
homework, labs and exams which require more sophisticated and creative
solutions.
Computer Requirements: The default CAD tools for all students are Cadence and Synopsys
electronic design automation tools. An example flow and a tutorial on the use
of these tools are available at the TA
Page. Since all the tools are Unix based, they can be accessed using any
X-server program from machines running on MS Windows. For your convenience, Cygwin that includes an X-server is installed on
all Windows machines on ECS computers in Marston 112 and 134. We also encourage
you to install and try Cygwin or xLiveCD on your own PCs. Off-campus
students are not required to do labs, but are required to do homework
simulations using Cadence and Synopsys tools. Web access to the course homepage
(this page) is assumed for all students.
Textbook (Required) : Digital Integrated Circuits, Jan M.
Rabaey, Anantha P. Chandrakasan, Borivoje Nikolic, Pearson Education,Prentice
Hall, 2nd Edition, 2003, ISBN 0130909963. Web Page for the book including
Powerpoint and PDF of all slides
Supplementary Readings:
Design of High Performance
Microprocessor Circuits, A. Chandrakasan, W. Bowhill, F. Fox, IEEE Press, 2000,
ISBN 078036001-X
CMOS VLSI Design: A Circuits and
Systems Perspective, 3rd Edition, Neil Weste, David Harris, Addison Wesley,
2003,ISBN: 0-321-14901-7
CMOS Digital Integrated Circuits:
Analysis and Design, 3rd Edition,Sung-Mo Kang,Yusuf Leblebici,McGraw-Hill,
2002, ISBN:0071196447
Chip Design for Submicron VLSI: CMOS
Layout and Simulation,1st Edition, John P. Uyemura,
Thomson,2005,ISBN:053446629X
A nice on-line VLSI course by Michael
Smith focusing on ASIC design is at: http://www.edacafe.com/books/ASIC/ASICs.php.
This site is very good for semi-custom design techniques using gate arrays and
programmable logic. It also provides good background on VHDL and Verilog
hardware description languages.
There will also be additional readings
from the academic, industrial and popular literature and various Web reading
assignments. These will all be announced in class with links and bibliographic
information provided on this Web page.
Homeworks: There will be about five homework assignments
which allow you to practice your analytical skills. Most of these will require
the use of the SPICE circuit simulators.
Labs : There will be four lab projects which allow
you to practice your design skills using computer aided design tools. These
labs are a substantial and memorable ;) part of the course. A variety of CAD
tools will be used for design and simulations. Lab 4 will be a final project
which will be worth double the value of the other labs. Note that each lab
builds on the previous ones.
Schedule (this WILL change throughout the initial
semester that it is offered)
|
Event |
Date
(For Fall 2006) |
Topics |
Notes |
HW-LAB schedule |
Reading |
|
Lecture 1 |
Sept 7 |
Introduction,
Objectives, Expectations, Logistics |
|
none |
|
|
Lecture 2 |
Sept 12 |
Design
Tools and Flows (demo by TA) |
|
||
|
Lecture 3 |
Sept 14 |
VLSI
Design: History, Trends, Principles, Metrics |
Chapter 1 |
||
|
Lecture 4 |
Sept 19 |
CMOS
Process and Layout |
Chapter 2, Insert A |
||
|
Lecture 5 |
Sept 21 |
CMOS
Devices: SPICE and deep sub-micron issues (demo
by TA) |
Hw1 --
Due |
Chapter 3 |
|
|
Lecture 6 |
Sept 26 |
The
Wire |
Chapter 4 |
||
|
Lecture 7 |
Sept 28 |
CMOS
Inverter: speed, power and scaling |
Chapter 5 |
||
|
Lecture 8 |
Oct 3 |
Static
CMOS Gates |
|
Chapter 6, RCN pp. 235-283 |
|
|
Lecture 9 |
Oct 5 |
Dynamic
CMOS Gates |
|
Chapter 6, RCN pp. 284-308 |
|
|
Lecture 10 |
Oct 10 |
Power
Estimation and Optimization |
Hw3
– Preview Lab1 -- Due |
Rabaey pp. 257-263; 309-323 |
|
|
Lecture 11 |
Oct 12 |
Exam
1 review |
Hw2 -- Due |
none. |
|
|
|
Oct 17 |
TA
review |
No lecture |
None |
None |
|
Exam 1 |
Oct 17 |
Covering
Lectures 1 through 11 |
|
Exam 1 |
Location: ELAB 304 Time: 7:00-9:00 pm |
|
Lecture 12 |
Oct 19 |
Sequential
Logic Circuits Part I |
Chapter 7, RCN pp. 325-353 |
||
|
Lecture 13 |
Oct 24 |
Sequential
Logic Circuits Part II |
|
Chapter 7, RCN pp. 354-372 |
|
|
Lecture 14 |
Oct 26 |
Implementation
Strategies for Digital ICs |
|
Chapter 8 |
|
|
Lecture 15 |
Oct 31 |
Interconnects |
Lab2 -- Due |
Chapter 9 |
|
|
Lecture 16 |
Nov 2 |
Advanced
Interconnects |
Hw3-Due |
||
|
Lecture 17 |
Nov 7 |
Timing
and Clocking |
|
Chapter 10, RCN pp.491-533 |
|
|
Lecture 18 |
Nov 9 |
Datapath
Design Part I |
Lab4
– Assigned (GRAD) |
Chapter 11, RCN pp. 559-593 |
|
|
Lecture 19 |
Nov 14 |
Datapath
Design Part II |
|
Chapter 11, RCN pp. 594-621 |
|
|
Lecture 20 |
Nov 16 |
Exam
2 review |
Lab4 – Assigned (UGRAD) |
None |
|
|
|
Nov 21 |
TA
review |
No lecture |
None Hw4 -- Due |
None |
|
Exam 2 |
Nov 21 |
Covering
Lectures 1 through 20 |
|
Exam 2 |
|
|
Lecture 21 |
Nov 28 |
Memory
Design Part I |
Chapter 12, RCN pp. 623-692 |
||
|
Lecture 22 |
Nov 30 |
Memory
Design Part II |
|
Chapter 12, RCN pp. 693-717 |
|
|
Lecture 23 |
Dec 5 |
Advanced
Topics |
|
See Lecture 23 |
|
|
Lecture 24 |
Dec 7 |
Conclusions
and Final Exam Review |
|
none. |
|
|
|
Dec 12 |
Homework
5 submission & solutions given |
No lecture |
Hw5
– Due |
none. |
|
|
Dec 19 |
Comprehensive |
|
|
For administrative information contact
the UMASS Video Instructional Program .
Homeworks are due 2 weeks after receipt. Homeworks should be mailed to Prof.
Burleson at the address on his web page. Do not fax your homework. Some
assignments will be submitted via email. Lateness penalties do not apply to
off-campus students. But don't fall behind!!
Off-campus students ARE NOT REQUIRED
TO DO LABS. HSPICE is required for all students for homework simulations.
Other information