This is a research project based at the VLSI Signal Processing Group at the University of Massachusetts at Amherst. It explores architectures, systems and tools for reconfigurable computing in communications applications. It builds on our previous work in array synthesis and modules for wireless systems, and various design projects for DSP and communications at the FPGA, ASIC and software levels. This work is very preliminary .
The project also involves collaborations on compilers and systems with the UMASS Computer Science Department and applications with the UMASS ECE Microwave Remote Sensing Lab and the Wireless Networking Lab. We are also working with international colleagues at Ecole Nationale Superieure des Telecommunications , Paris, France, and the Pusan National University , Pusan, South Korea through the IDES project .
We have developed a number of parameterized, module generators for regular computations found in DSP and wireless communications. These include LZ compression, PVQ compression/decompression, Reed-Solomon encoding and decoding, RSA and DES encryption. These architectures are described in a format which preserves regularity and allows a broad range of design alternatives to be explored and simulated in Verilog. These techniques are particularly appropriate for reconfigurability due to locality, heavy pipelining, fine-grained parallelism, scalability, and a range of area/performance tradeoffs for the same architecture. Weaknesses include I/O requirements, coping with irregularity and complex timing. Module generators were developed for ASICs to allow re-use, scalability and ease of design. These are exactly the same attributes we need in a reconfigurable system where the modules are designed "on the fly".
We have developed a novel motion estimation algorithm which uses dynamically reconfigurable hardware to adapt to the image on a frame-by-frame basis. We have also developed a Takagi multiplier for RSA encryption which uses configuration to hard-wire the key and modulus resulting in significant power, area and speed improvment.
The objective of this research is to develop methods and tools for the design and programming of programmable logic systems for low-power signal processing applications. The research consists of four aspects. The first is the modeling of power consumption in programmable logic for signal processing. The second is the optimization of power consumption with techniques at the architectural, algorithmic and system level. The third aspect is the verification of these models and optimizations with actual power measurements on real signal processing applications using commercial FPGAs (both Altera and Xilinx). The applications are an MPEG2 coder and a wireless receiver using an FFT. The fourth aspect is the investigation of new FPGA circuits, architectures, design methods and CAD tools which are more power efficient.
We are exploring dynamically reconfigurable FPGAs from both Atmel and Xilinx for power savings. The basic idea is to generalize the idea of sub-system power-down to adapt the architecture dynamically to a lower power mode. Since both voltage-scaling and selective clock-gating are tricky with FPGAs, we are looking at other more architectural techniques. In particular, we propose to modify algorithm parameters and power/performance tradeoffs available using the module generators described above. The new FPGA architectures also allow partial reconfiguration with portions of the circuit continuing to function while others are loaded. This should allow more "graceful" methods of power-down.
High-performance controllers are found in numerous network applications and often are the bottleneck to higher speed communications. Protocols, in particular, are usually described as Finite State Machines (FSMs) and implemented in microcontrollers. As network protocols become more sophisticated in order to deal with the complexity of multimedia communications over heterogeneous networks, the corresponding state machines become significantly more complicated. In addition, they require the ability to be re-programmed, both due to evolving standards as well as adaptation to on-the-fly network changes. Wireless networks, in particular, require complex protocols due to the limited bandwidth and noisy behavior inherent in the wireless channel. Thus, there is a need for high-performance, but still programmable, implementations of complex finite state machines.
We propose to use reconfigurable Field Programmable Gate Arrays for network FSMs due to their inherent parallelism and their ease of on-the-fly reconfiguration. Other FSM implementation techniques are typically 1) Microcontrollers and 2) Application-Specific Integrated Circuits (ASIC). Microcontrollers are severely limited in their parallelism and inefficiencies due to general-purpose hardware while ASICs suffer from a lack of programmability and substantial design costs.
We propose a new approach based on a novel compiler framework with a new intermediate format which allows code generation for hetergeneous architectures. We will use this along with the module libraries discussed above to provide a unified approach to the design of DSP software and FPGA hardware which is both high-performance and power efficient. Within the modular compiler framework, we will make use of existing VHDL, FPGA and DSP tools for specific front-ends, optimizations and target architectures. Existing co-synthesis systems will be modified to account for dynamic and partial reconfiguration. Code generation for multiple heterogeneous cores (DSP, RISC, microcontroller) will be developed as well as partitioning algorithms between cores and FPGAs.
We propose a novel architecture for adaptive computing applications consisting of an array of DSP cores and memory with a large resource of reconfigurable FPGAs for application-specific computations and interconnection. Future semiconductor technology will allow such a system to be implemented on a single VLSI chip, but initially we will develop a hardware emulation system based on existing DSP, microcontroller and FPGA emulation systems which allow near real-time system demonstrations. Architectural explorations will be used to identify features and configurations which best support adaptive computing for both special-purpose and general-purpose applications.
Existing FPGAs are designed for the implementation of random logic and desipte recent improvements, they really need to be re-designed for adaptive computing. Logic cells, clocking, interconnect and memory all need to be re-evaluated in the context of the target class of computations. External interfaces to memory and processors, as well as reconfiguration methods, including self reconfiguration, also need to be explored.
The emulation system will be demonstrated in an actual wireless LAN testbed currently under construction at the University of Massachusetts. We are also currently developing an FPGA-based data acquisition system for radar remote sensing with Microwave Remote Sensing Lab at UMASS. This system is based on Giga-Ops and Xilinx technology and will be embedded in an unmanned airborne vehicle thus having significant power, size and reliability constraints. For details, see ``An FPGA-based Data Acquisition System for a 95 Ghz W-band Radar'' , 1997 Intl. Conference on Acoustics, Speech and Signal Processing (ICASSP) A third application area is the development of co-processors for path-planning in robotics and vehicle control. This is a collaboration with the UMASS Computer Science department and involves the co-development of algorithms and architectures to support a new biologically motivated approach to robust real-time path optimization.
A current undergraduate design project involves the design of a wireless network co-processor which can reconfigure between a Lempel-Ziv data compression and an RSA encryption/decryption. The project uses Altera FLEX10K FPGAs and a PIC microcontroller. More details on this project can be found at Lempel-Ziv Design Project . at ENST, Paris. The project involves students at ENST/Paris, UMASS/Amherst and Pusan National University. The project is entirely documented on the Web to allow the results to be used by students at all three schools. This is part of the IDES (International Design of Embedded Systems) Project .
From the three applications we expect to develop a set of benchmarks on which to test and compare theories, techniques and tools for adaptive computing. This could lead to a larger effort involving other applications and tools from other research groups.
Prof. Wayne Burleson is directing this research. Students involved in this project include: