                Core name: Xilinx LogiCORE Virtex-4 FX FPGA RocketIO Multi-Gigabit Transceiver Wizard
                Version: 1.7
                Release Date: April 19, 2010


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This document contains the following sections:

1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer

================================================================================

1. INTRODUCTION

For the most recent updates to the IP installation instructions for this core,
please go to:

   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:

   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm



This file contains release notes for the Xilinx LogiCORE IP Virtex-4 FX FPGA Multi-Gigabit Transceiver Wizard v1.7
solution. For the latest core updates, see the product page at:

  http://www.xilinx.com/products/ipcenter/V4_RocketIO_Wizard.htm

2. NEW FEATURES

   - ISE 12.1 software support

3. SUPPORTED DEVICES

   - xc4vfx20, xc4vfx40, xc4vfx60, xc4vfx100, xc4vfx140, xq4vfx60, xq4vfx100


4. RESOLVED ISSUES

   - Fixed CR 475256, 475189, 471103, 470068, 451281, 451174

5. KNOWN ISSUES

   The following are known issues for v1.7 of this core at time of release:

   - The GT11 smartmodel will produce RX Disparity errors due to rounding
     problems for some reference clock periods. If, in simulation, the MGT
     wrapper locks successfully but shows numerous disparity errors, edit
     testbench/example_tb.v(hd) and increment or decrement the REFCLK period
     by 0.01. This is the case for Fibre Channel 2x and 4x, for example, where
     the refclk period must be changed from 4.71 ns to 4.7 ns.

   - OOB signaling is not supported in simulation.

   - The example design does not currently include blocks to demonstrate
     Channel Bonding and Clock Correction.

   - Setting the comma alignment (Wizard page 4) smaller than the data path
     width allows incoming data to be aligned to multiple positions. The
     example design does not account for this and may indicate errors even
     though data is being received correctly.

   - The example designs provide little support for CRC. The wrapper will
     configure the CRC blocks, but additional work is required to test and
     connect the logic.

   - Be careful to use run lengths supported by your silicon version when
     selecting 'no encoding'/'no decoding' on Wizard page 3.

   - Example designs for configurations using different data widths for TX
     and RX may not function.

   - Configurations using different line rates for TX and RX on the same MGT
     have not been thoroughly tested, and may not work.

   - Multilane protocol files such as XAUI may not turn on all required MGTs
     in some packages. If your wrapper is missing lanes, please recustomize
     your wrapper and select the needed MGTs on Wizard page 2.

   - 64B/66B options have not been tested in hardware. Devices supporting
     64B/66B were not available at development time.


  The most recent information, including known issues, workarounds, and
  resolutions for this version is provided in the IP Release Notes Guide
  located at

     www.xilinx.com/support/documentation/user_guides/xtp025.pdf

6. TECHNICAL SUPPORT

   To obtain technical support, create a WebCase at www.xilinx.com/support.
   Questions are routed to a team with expertise using this product.

   Xilinx provides technical support for use of this product when used
   according to the guidelines described in the core documentation, and
   cannot guarantee timing, functionality, or support of this product for
   designs that do not follow specified guidelines.


7. CORE RELEASE HISTORY

Date        By            Version      Description
================================================================================
04/19/2010  Xilinx, Inc.  1.7          ISE 12.1 support, bug fixes 
03/24/2008  Xilinx, Inc.  1.6          10.1 support, bug fixes
08/15/2007  Xilinx, Inc.  1.5          9.2i support
03/01/2007  Xilinx, Inc.  1.4          Bug fixes, new protocol support
11/30/2006  Xilinx, Inc.  1.3          Flexible UNISIMS support, bug fixes
06/06/2006  Xilinx, Inc.  1.1          Extensive enhancements and fixes
================================================================================

8. Legal Disclaimer

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