################################################################################
##$Date: 2010/06/25 15:58:01 $
##$RCSfile: example_mgt_top_ucf.ejava,v $
##$Revision: 1.2 $
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##   ____  ____ 
##  /   /\/   / 
## /___/  \  /    Vendor: Xilinx 
## \   \   \/     Version : 1.7
##  \   \         Application : RocketIO Wizard 
##  /   /         Filename : example_mgt_top.ucf
## /___/   /\     Timestamp : 02/08/2005 09:12:43
## \   \  /  \ 
##  \___\/\___\ 
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx RocketIO Wizard
##
## Device:  xc4vfx20
## Package: ff672

#Set stepping configuration for CES4, CES4S, or STEP0/1
CONFIG STEPPING = "0";


################################## Clock Constraints ##########################

# Reference clock contraint for MGTs on the left edge of the V4 device
NET sata_core_i/sata_phy_i/refclk1_i PERIOD = 6.67 ns;

# DRP Clock Constraint
NET sata_core_i/sata_phy_i/drp_clk_i PERIOD = 20.0 ns;

NET clk_100 PERIOD = 10.0 ns;

NET TX_SYSTEM_RESET_IN  LOC=K8;   #GPIO_SW_W
NET RX_SYSTEM_RESET_IN  LOC=M6;   #GPIO_SW_E

NET CLK_100_IN LOC = AB14;


NET START							LOC=L10; #GPIO_SW_S
NET LINKUP							LOC=F14; #LED GPIO_LED_3

#Serial port debugging
NET SERIAL_TX LOC = T8;
NET SERIAL_RX LOC = T4;
NET SERIAL_RX IOSTANDARD = LVCMOS33;
NET SERIAL_TX IOSTANDARD = LVCMOS33;

######################### mgt clock module constraints ########################

NET UPPER_MGTCLK_PAD_N_IN  LOC=L1;
NET UPPER_MGTCLK_PAD_P_IN  LOC=K1;

INST sata_core_i/sata_phy_i/mgt_clock_module_i/upper_gt11clk_mgt_inst LOC = GT11CLK_X1Y1;
INST sata_core_i/sata_phy_i/mgt_clock_module_i/upper_gt11clk_mgt_inst SYNCLK1OUTEN = ENABLE;
INST sata_core_i/sata_phy_i/mgt_clock_module_i/upper_gt11clk_mgt_inst SYNCLK2OUTEN = DISABLE;

################################# mgt wrapper attributes ######################

INST sata_core_i/sata_phy_i/rocketio_i/MGT0 TXCLK0_INVERT_PMALEAF=TRUE;
INST sata_core_i/sata_phy_i/rocketio_i/MGT1 TXCLK0_INVERT_PMALEAF=TRUE;

################################# mgt wrapper constraints #####################

##-------------------- Set placement for MGT0 ------------
INST sata_core_i/sata_phy_i/rocketio_i/MGT0 LOC=GT11_X1Y2;
##-------------------- Set placement for MGT1 ------------
INST sata_core_i/sata_phy_i/rocketio_i/MGT1 LOC=GT11_X1Y3;



