################################################################################
##$Date: 2010/06/25 15:58:01 $
##$RCSfile: example_mgt_top_ucf.ejava,v $
##$Revision: 1.2 $
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##   ____  ____ 
##  /   /\/   / 
## /___/  \  /    Vendor: Xilinx 
## \   \   \/     Version : 1.7
##  \   \         Application : RocketIO Wizard 
##  /   /         Filename : example_mgt_top.ucf
## /___/   /\     Timestamp : 02/08/2005 09:12:43
## \   \  /  \ 
##  \___\/\___\ 
##
##
## USER CONSTRAINTS FILE FOR MGT WRAPPER EXAMPLE DESIGN
## Generated by Xilinx RocketIO Wizard
##
## Device:  xc4vfx20
## Package: ff672

#Set stepping configuration for CES4, CES4S, or STEP0/1
CONFIG STEPPING = "0";


################################## Clock Constraints ##########################

# Reference clock contraint for MGTs on the left edge of the V4 device
NET refclk1_i PERIOD = 6.67 ns;



# DRP Clock Constraint
NET drp_clk_in_i PERIOD = 20.0 ns;


  

######################## locs for top level ports ######################


#Push button connections for resets
NET TX_SYSTEM_RESET_IN  LOC=AA3;   #BUTTON
NET RX_SYSTEM_RESET_IN  LOC=AA4;   #BUTTON

#Oscillator for DRP CLK
NET DRP_CLK_IN      LOC=AB14;  #OSCILLATOR

#RXLOCK and TXLOCK pins (assumes layout of ML42x MGT eval board, with 20 LEDs)
NET MGT0_RXLOCK_OUT          LOC=AC9;   #LED
NET MGT0_TXLOCK_OUT          LOC=AD8;   #LED
NET MGT1_RXLOCK_OUT          LOC=AD9;   #LED
NET MGT1_TXLOCK_OUT          LOC=V6;   #LED



######################### mgt clock module constraints ########################


NET UPPER_MGTCLK_PAD_N_IN  LOC=L1;
NET UPPER_MGTCLK_PAD_P_IN  LOC=K1;

INST mgt_clock_module_i/upper_gt11clk_mgt_inst LOC = GT11CLK_X1Y1;
INST mgt_clock_module_i/upper_gt11clk_mgt_inst SYNCLK1OUTEN = ENABLE;
INST mgt_clock_module_i/upper_gt11clk_mgt_inst SYNCLK2OUTEN = DISABLE;


################################# mgt wrapper attributes ######################

INST rocketio_i/MGT0 TXCLK0_INVERT_PMALEAF=TRUE;
INST rocketio_i/MGT1 TXCLK0_INVERT_PMALEAF=TRUE;

################################# mgt wrapper constraints #####################

##-------------------- Set placement for MGT0 ------------
INST rocketio_i/MGT0 LOC=GT11_X1Y2;
##-------------------- Set placement for MGT1 ------------
INST rocketio_i/MGT1 LOC=GT11_X1Y3;



