##############################################################
#
# Xilinx Core Generator version 14.2
# Date: Wed Aug 14 16:24:52 2013
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:v4fx_mgtwizard:1.7
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc4vfx20
SET devicefamily = virtex4
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff672
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -10
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Virtex-4_FX_FPGA_RocketIO_Multi-Gigabit_Transceiver_Wizard family Xilinx,_Inc. 1.7
# END Select
# BEGIN Parameters
CSET bandgapsel=false
CSET biasressel=false
CSET bypass_rx_fifo=true
CSET bypass_tx_fifo=true
CSET calblock_version=1.4.1
CSET cb_limit=16
CSET cb_one_shot_mode=false
CSET cb_sequence_1_1=00000000
CSET cb_sequence_1_1_disp_err=false
CSET cb_sequence_1_1_k=false
CSET cb_sequence_1_1_mask=false
CSET cb_sequence_1_2=00000000
CSET cb_sequence_1_2_disp_err=false
CSET cb_sequence_1_2_k=false
CSET cb_sequence_1_2_mask=false
CSET cb_sequence_1_3=00000000
CSET cb_sequence_1_3_disp_err=false
CSET cb_sequence_1_3_k=false
CSET cb_sequence_1_3_mask=false
CSET cb_sequence_1_4=00000000
CSET cb_sequence_1_4_disp_err=false
CSET cb_sequence_1_4_k=false
CSET cb_sequence_1_4_mask=false
CSET cb_sequence_2_1=00000000
CSET cb_sequence_2_1_disp_err=false
CSET cb_sequence_2_1_k=false
CSET cb_sequence_2_1_mask=false
CSET cb_sequence_2_2=00000000
CSET cb_sequence_2_2_disp_err=false
CSET cb_sequence_2_2_k=false
CSET cb_sequence_2_2_mask=false
CSET cb_sequence_2_3=00000000
CSET cb_sequence_2_3_disp_err=false
CSET cb_sequence_2_3_k=false
CSET cb_sequence_2_3_mask=false
CSET cb_sequence_2_4=00000000
CSET cb_sequence_2_4_disp_err=false
CSET cb_sequence_2_4_k=false
CSET cb_sequence_2_4_mask=false
CSET cb_sequence_is_control_block=false
CSET cb_sequence_length=8
CSET cc_fifo_lower_bound=28
CSET cc_fifo_upper_bound=40
CSET cc_sequence_1_1=01111100
CSET cc_sequence_1_1_disp_err=false
CSET cc_sequence_1_1_k=true
CSET cc_sequence_1_1_mask=false
CSET cc_sequence_1_2=10010101
CSET cc_sequence_1_2_disp_err=false
CSET cc_sequence_1_2_k=false
CSET cc_sequence_1_2_mask=false
CSET cc_sequence_1_3=10110101
CSET cc_sequence_1_3_disp_err=false
CSET cc_sequence_1_3_k=false
CSET cc_sequence_1_3_mask=false
CSET cc_sequence_1_4=10110101
CSET cc_sequence_1_4_disp_err=false
CSET cc_sequence_1_4_k=false
CSET cc_sequence_1_4_mask=false
CSET cc_sequence_2_1=10111100
CSET cc_sequence_2_1_disp_err=false
CSET cc_sequence_2_1_k=true
CSET cc_sequence_2_1_mask=false
CSET cc_sequence_2_2=01001010
CSET cc_sequence_2_2_disp_err=false
CSET cc_sequence_2_2_k=false
CSET cc_sequence_2_2_mask=false
CSET cc_sequence_2_3=01001010
CSET cc_sequence_2_3_disp_err=false
CSET cc_sequence_2_3_k=false
CSET cc_sequence_2_3_mask=false
CSET cc_sequence_2_4=01111011
CSET cc_sequence_2_4_disp_err=false
CSET cc_sequence_2_4_k=false
CSET cc_sequence_2_4_mask=false
CSET cc_sequence_is_control_block=false
CSET cc_sequence_length=32
CSET column_location=X1
CSET comma_10bit_mask=1111111111
CSET comma_alignment_boundary=4
CSET component_name=rocketio
CSET cycle_limit_sel=00
CSET dclk_rate=50.000
CSET detect_minus_comma=true
CSET detect_minus_comma_alignment=true
CSET detect_plus_comma=true
CSET detect_plus_comma_alignment=true
CSET disable_cccb_arbitrator=false
CSET enable_drp_port=true
CSET enable_external_rxusrclk=false
CSET enable_external_txusrclk=false
CSET enable_rx_slide=false
CSET enable_rxclkstable=true
CSET enable_txclkstable=true
CSET fdet_hys_cal=010
CSET fdet_hys_sel=001
CSET fdet_lck_cal=101
CSET fdet_lck_sel=111
CSET irefbiasmode=11
CSET loopback_mode=OFF
CSET loopcal_wait=00
CSET minus_comma_value=0101111100
CSET plus_comma_value=1010000011
CSET pmaclkenable=true
CSET pmacorepwrenable=true
CSET pmaireftrim=0111
CSET pmavbgctrl=00000
CSET pmavreftrim=0111
CSET power_enable=true
CSET protocol_file=sata_I
CSET refclk1_source=UPPER_MGTCLK
CSET refclk2_source=LOWER_MGTCLK
CSET rx_crc_init_value=00000000
CSET rx_crc_input_bus_width=32
CSET rx_data_width=32
CSET rx_decoding=8B10B
CSET rx_line_rate=1.500
CSET rx_lock_to_ref=false
CSET rx_oob_threshold=10
CSET rx_reference_clock=REFCLK1
CSET rx_reference_clock_rate=150.0
CSET rxactst=false
CSET rxafeeq=000000000
CSET rxafepd=false
CSET rxafetst=false
CSET rxapd=false
CSET rxcmadj=01
CSET rxcpsel=false
CSET rxcptst=false
CSET rxctrl1=200
CSET rxcycle_limit_sel=00
CSET rxeq=4000000000000000
CSET rxfdcal_clock_divide=NONE
CSET rxfdet_hys_cal=010
CSET rxfdet_hys_sel=001
CSET rxfdet_lck_cal=101
CSET rxfdet_lck_sel=100
CSET rxfecontrol1=00
CSET rxfecontrol2=000
CSET rxfetune=01
CSET rxlkadj=00000
CSET rxlkapd=false
CSET rxloopcal_wait=00
CSET rxloopfilt=1111
CSET rxpd=false
CSET rxpddtst=true
CSET rxrcpadj=010
CSET rxrcppd=false
CSET rxribadj=11
CSET rxrpdpd=false
CSET rxrsdpd=false
CSET rxslowdown_cal=00
CSET rxvco_ctrl_enable=true
CSET rxvcodac_init=0001010001
CSET silicon_version=PRODUCTION_STEP_0_or_1
CSET slowdown_cal=00
CSET sync_tx_for_low_skew=false
CSET tx_crc_init_value=00000000
CSET tx_crc_input_bus_width=32
CSET tx_data_width=32
CSET tx_encoding=8B10B
CSET tx_line_rate=1.500
CSET tx_reference_clock=REFCLK1
CSET tx_reference_clock_rate=150.0
CSET txapd=false
CSET txarefbiassel=true
CSET txcpsel=true
CSET txctrl1=200
CSET txdat_prdrv_dac=111
CSET txdat_tap_dac=10110
CSET txdigpd=false
CSET txfdcal_clock_divide=NONE
CSET txhighsignalen=true
CSET txloopfilt=0101
CSET txlvlshftpd=false
CSET txpd=false
CSET txpost_prdrv_dac=111
CSET txpost_tap_dac=00001
CSET txpost_tap_pd=true
CSET txpre_prdrv_dac=111
CSET txpre_tap_dac=00000
CSET txpre_tap_pd=true
CSET txtermtrim=1100
CSET use_calblock=true
CSET use_channel_bonding=false
CSET use_clock_correction=false
CSET use_comma_align=true
CSET use_digital_cdr=false
CSET use_mgt_y0=false
CSET use_mgt_y1=false
CSET use_mgt_y10=false
CSET use_mgt_y11=false
CSET use_mgt_y2=true
CSET use_mgt_y3=true
CSET use_mgt_y4=false
CSET use_mgt_y5=false
CSET use_mgt_y6=false
CSET use_mgt_y7=false
CSET use_mgt_y8=false
CSET use_mgt_y9=false
CSET use_rx_crc=false
CSET use_rx_internal_ac_coupling=true
CSET use_rx_oob=true
CSET use_two_cb_sequences=false
CSET use_two_cc_sequences=true
CSET use_tx_crc=false
CSET use_tx_low_slew_rate=true
CSET use_tx_oob=true
CSET valid_8b10b_rxchariscomma_only=true
CSET vco_ctrl_enable=true
CSET vcodac_init=0001010001
CSET vrefbiasmode=11
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-07-21T06:31:03Z
# END Extra information
GENERATE
# CRC: 3be1e0ed
