Compilation for
Parallel Soft Processors
The recent development of soft processor architectures has significantly
expanded the application space of FPGAs. Although
initial soft processor architectures have been well received, little work has
been performed in integrating multiple soft processors onto an FPGA. In this
work, we are developing a parallel processing environment for multiple soft
processors which incorporates parallel compilation and inter-processor
communication structures. Our approach is targeted to existing FPGA
architectures and takes advantage of the plentiful logic, multiplier, and
embedded memory resources located within contemporary FPGAs.
Our approach is application driven and will assist in the evaluation of FPGA applications.
To fully test our approach, communications, radar processing, and image
processing benchmarks that are under development by the Reconfigurable
Computing Group are being used. Our new multiprocessor systems are based on existing
soft processor designs, mapped to Cyclone II devices using Quartus
II, and tested on an Altera DE2 board.
This work is funded by Altera
Corporation.