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Introduction
to the Adaptive Reed Solomon Errors and Erasures Algorithm
Contact: Russell
Tessier (tessier@ecs.umass.edu)
Adaptive Reed Solomon Errors-and-Erasures Algorithm
Information regarding
the development of a hardware implementation of the adaptive Reed Solomon
errors and erasures algorithm is provided in:
[1] L. Atieno, J. Allen,
D. Goeckel, and R. Tessier,
An Adaptive
Reed-Solomon Errors-and-Erasures Decoder, in the Proceedings
of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays,
Monterey, CA, February 2006.
Hardware
Implementation
A zip file containing
RTL code which implements an adaptive RS errors-and-erasures decoder is
available here. Associated Verilog, MIF, and include files are included.
Scaling the Design
The RTL code for
each design can be scaled by modifying the value of K in the file top_rs_decode.v (`define K217, etc). Testbench and simulation files for each value of K are
included in the directory. The value K =239 is used as the default. This
design will compile without errors using Quartus
II version 5.1 using the project file located in the associated zip file. Valid
K values are 217, 221, 225, 233, 237, and 239. Design size varies from
~14,000 LUTs for n=239 to ~27,000 LUTs for K=217.
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