UMass RCG HDL Benchmark Collection

A suite of various testbenches collected and developed from projects at the University of Massachusetts


This collection of benchmarks has been developed for use in testing and performance analysis of various parameters, including area, speed and power, of designs mapped to FPGA architectures. This page will evolve as research continues and more benchmarks and information will be added as they are collected. These designs are intended to be freely available and may not be included in any commercial application. Several of the designs have been adapted from the OpenCores benchmark suite (

The designs are currently being used in research at UMass to evaluate the power consumption properties of custom FPGA circuits versus microprocessors. Target architectures include the Stratix FPGA architecture from Altera and the ST230 VLIW Microprocessor from ST Microelectronics. Although the current synthesis environment used on the designs is Altera Quartus II, the RTL Verilog and VHDL designs could likely be easily ported to other FPGA or ASIC synthesis environments. This research has been partially funded by ST Microelectronics and Altera.

The AVA, ASOVA, and Reed Solomon designs were developed by: Jonathan Allen, David Howland, Kevin Oo TinMaung, Atchuthan Perinkulam, Lilian Atieno, Jian Liang, and Sriram Swaminathan of the UMass Reconfigurable Computing Group.

Contact: Jonathan Allen (

More information on the UMass Amherst Reconfigurable Computing Group can be found here.


Current Benchmarks

The current collection of testbenches includes:

  • FIR Filter
  • FDCT transform  
  • JPEG encoding unit  
  • ASOVA turbo code decoder 
  • AVA communications decoder
  • Adaptive Reed-Solomon decoder

These designs have been optimized to make use of structures within the Stratix architecture, including (but not limited to) maximum parallelism and the use of embedded structures (DSP blocks, embedded memories).


Installation and Usage Instructions

Detailed documentation of each design is included in many of the files as comments. A brief overview of general usage is provided below.

Components of the Designs

Each design is provided as a zipped archive (below). The contents of the archive in general are:

  • A collection of design files, in either Verilog (.v) or VHDL (.vhd) format.
  • A testbench file (.vt or .vht), which instantiates the top level module, feeds sample data through the design, and checks the outputs for correctness.
  • One or more Quartus Project Files, which can be used to load the designs into Quartus for further analysis/development.
  • One or more Quartus vector waveform simulation files (.vwf) corresponding to the testbench files.


The user must have installed and licensed versions of Quartus 5.1 or later and Mentor Graphics ModelSim-Altera 6.0e or later (Typically distributed with Quartus, for running .vt testbench files). . Earlier versions of these tools may also work although we have not tested the designs with them.

Installation and Usage Instructions

Note: For the sake of brevity, instructions will be outlined for the setup and use of the testbenches within Quartus will be provided, along with brief instructions for running the testbench alone via Verilog XL, part of the Cadence VLSI design package. If the user needs to make modifications or would like to use the designs in a different manner, please refer to the documentation of the Quartus tools available from Altera's website. Note that current testbenches are probably not sufficient to fully characterize circuit switching. The testbenches would have to be enhanced to allow for accurate power analysis of the designs.

  1. Unpack the archive to your project directory.
  2. Open the Quartus top level project file (specified for each design below). Users may also choose to create their own project, and import the design files directly. Make sure to pay attention to which file is the top level design. Refer to the Quartus documentation for further help.
  3. Quartus by itself is incapable of running testbenches. To run the testbench, Quartus used ModelSim. To set this up, go to the Assignments>EDA Tool Settings menu. In the settings menu, click on EDA Tool Settings>Simulation. This will bring up the EDA Simulation settings on the right side of the settings window. Select ModelSim-Altera, either Verilog or VHDL output, depending on the language of the design. Check the box labeled "Run gate level simulation automatically after compilation". Click on the "Gate Level Simulation Settings" box. In the window which pops up, choose "Testbench Mode", and specify the testbench file and top level module. Close the window. Additional settings can be adjusted as needed. Refer to the Quartus documentation for more info.
  4. After the project has been set up, compile the top level design by either clicking on the compile button in the toolbar at the top, or selecting Processing>Start Compilation from the menu at the top. When the design has finished compilation, ModelSim-Altera will be launched, and the testbench will be run, with results displayed. The testbench can also be run at any time after compilation by choosing Tools>Run EDA Simulation Tool from the menu.

Verilog XL

To run the testbench in Verilog XL (assuming the user has the Cadence tools setup correctly):

  1. Unpack the archive.
  2. Create a text file, <filename>.cfg, listing all of the design files included in the project, beginning with the testbench file. An example file for the FIR can be found here.
  3. At the Unix prompt, type "verilog -f <filename>.cfg

The design will then be compiled and run, with outputs displayed to the terminal.



FIR Filter

  • Simple digital finite impulse response filter, with scalable number of taps and configurable coefficient values.
  • Design uses 822 LUTs and 25 DSP blocks in a Stratix device
  • The number of taps in the design can be modified by changing the TAPS parameter in fir_filter.v
  • Top Level Module: fir_filter in fir_filter.v
  • TestBench File: fir_filter_square.vt
  • TestBench Description: Loads in coefficient values for an averaging filter, weight scaling with proximity, and runs a square wave through.
  • Archive: 


  • Forward Discrete Cosine Transform, outputs results serially in zigzag order.
  • Developed by Richard Herveille. See for more info.
  • Design uses 2205 LUTs, 16,640 memory bits, and 128 DSP blocks in a Stratix device
  • Top Level Module: fdct in fdct.v
  • TestBench File: bench_top.vt
  • Archive:


ASOVA turbo code decoder

  • Communications error correction decoder based on turbo codes which implements the adaptive soft-output Viterbi algorithm.
  • Developed by Dr. Jian Liang as part of his PhD thesis. Additional information on the design can be found here.
  • NMAX = 4 design uses 1,632 LUTs, 23,552 memory bits, and 0 DSP blocks in a Stratix device.
  • Larger versions of the design can be made by following directions here.
  • Top Level Module: turboSRAM.v
  • TestBench File: turboSRAM.vt
  • Archive:

AVA Decoder

  • Communications error correction decoder, implementing the adaptive Viterbi algorithm.
  • Developed by Sriram Swaminathan as part of his Masters thesis. Additional information on the design can be found here.
  • K = 10 design uses about ~12,000 LUTs, 0 memory bits, and 0 DSP blocks.
  • Top Level Module: ava in cpe0lce.vhd and cpe0lca.vhd
  • TestBench File: ava.vt
  • Archive:

Reed-Solomon Decoder

  • Reed-Solomon (255,n) decoder system.
  • Developed by Lilian Atieno as part of her Masters thesis. Additional information on the design can be found here.
  • K = 239 design uses ~14,000 LUTs, ~48,000 memory bits, and 13 DSP blocks.
  • Larger versions of the design can be made by following directions here.
  • Top Level Module: top_rs_decode.v
  • TestBench File: top_rs_decode239.vt, where 239 is the default parameter for K. As explained here, other values of K are possible.
  • Archive:


This page was created by Jonathan Allen. Last updated 9/4/06