Welcome to the 697FF Course Home Page. This serves as the syllabus for the course. The URL is: http://www.ecs.umass.edu/ece/tessier/courses/697ff/
Instructor: Russell Tessier, Associate Professor, Department of Electrical and Computer Engineering, tel: 413-545-0160, email: tessier 'at' ecs.umass.edu Office Hours : Tue Th 2:30-3:30
For further information about Reconfigurable computing at UMass, click here
Recent advances in VLSI technology have given rise to a new class of computer architectures which take advantage of application-level parallelism. These reconfigurable computers can be quickly customized at the hardware level to perform exactly the computation required in hardware, overcoming the fixed hardware configurations found in many contemporary microprocessors. In this class, we investigate the state-of-the-art in reconfigurable computing both from a hardware and software perspective. The desire to efficiently solve important problems drives reconfigurable computing. Consequently, throughout this class we will discuss several numeric and signal processing applications and the characteristics that make them attractive to reconfigurable computing platforms. Initially, we review in detail the basic building blocks of most reconfigurable computers, field-programmable gate arrays (FPGAs). The characteristics of FPGA VLSI architecture such as the organization of device logic and interconnection resources are examined to quantify hardware limitations. These physical limitations are then contrasted with computer-aided design issues such as the selection of circuit component locations in devices (the placement problem) and subsequent circuit interconnection between components (the routing problem). While discrete FPGA devices offer an abundance of usable logic, most current reconfigurable computing applications require hardware configurations of multiple FPGAs and memory components organized in a computing system. As a final step, we focus on the architecture for existing multi-FPGA systems and on compilation techniques for mapping applications described in a hardware description language to reconfigurable hardware. Specific contemporary reconfigurable computing systems are examined to identify existing system limitations and to highlight opportunities for research. (3 credits)
Prerequisites: Courses ECE221 (Intro to Digital and Computer Systems) and ECE232 (Hardware Organization and Design) are prerequisites for this class. Experience in ECE558 (Intro to VLSI Design) and ECE568 (Computer Architecture) may be helpful in understanding some of the course material but are not required. UMass undergraduates may take this course with the instructor's permission.
Grading: Homework (25%), Final Project (40%), Mid-Term (25%), Class participation/effort (10%).
Honesty Policy: Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course.
Computer Requirements: On-campus students will be doing labs using CAD software on UNIX workstations and PCs.
Course text (optional): FPGA-based System Design, Wayne Wolf, Prentice Hall, 2004, ISBN: 0-13-142461-0
Reference Material: Research papers will be suggested reading for each class to help stimulate discussion. Reconfigurable Computing and Digital Signal Processing by Tessier and Burleson and The Role of FPGAs in Reprogrammable Systems by Scott Hauck provide a good introduction to reconfigurable systems.
Homeworks : There will be three homework assignments that involve the development and use of CAD tools for reconfigurable computing including VPR, an academic FPGA place and route system. Students will also be required to transcribe notes from one lecture into a formal document.
Problem Set 1 Problem Set 2 Problem Set 3Course Project : This page provides provides information regarding the course project.
Course Philosophy : My goal is for students to become familiar with the state-of-the-art in reconfigurable computing. During the course open research problems in the field will be noted and students will have the opportunity to begin preliminary investigation of these issues through classroom projects.
Schedule (this WILL change
throughout the semester )
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Event |
Fall 06 |
Topics |
Notes |
Reading |
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Lecture 1 |
Sept 7 |
Introduction, Objectives, Expectations, Logistics |
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Lecture 2 |
Sept 14 |
Field Programmable Gate Arrays I |
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Lecture 3 |
Sept 19 |
Field Programmable Gate Arrays II |
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Lecture 4 |
Sept 21 |
FPGA Placement |
Marquardt paper , Tessier PhD thesis, Chapter 4 , entire thesis (optional) |
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Lecture 5 |
Sept 26 |
FPGA Routing |
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Lecture 6 |
Sept 28 |
Contrasting Processors: Fixed and Reconfigurable |
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Lecture 7 |
Oct 3 |
Coarse-grained Reconfigurable Devices |
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Lecture 8 |
Oct 10 |
Reconfigurable Systems I |
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Lecture 9 |
Oct 12 |
Reconfigurable Systems II |
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Lecture 10 |
Oct 17 |
Security for Embedded Reconfigurable Systems |
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Lecture 11 |
Oct 19 |
Logic Emulation |
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Lecture 12 |
Oct 24 |
Multi-FPGA System Software |
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Lecture 13 |
Oct 26 |
Reconfigurable Computing Applications I |
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Lecture 14 |
Oct 31 |
Reconfigurable Computing Applications II |
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Lecture 15 |
Nov 2 |
Reconfigurable Coprocessors |
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Lecture 16 |
Nov 7 |
Mid-Term Review |
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Lecture 17 |
Nov 9 |
Dynamic Reconfiguration I |
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Lecture 18 |
Nov 14 |
Dynamic Reconfiguration II |
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Lecture 19 |
Nov 16 |
Dynamically Reconfigurable Adaptive Viterbi Decoder |
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Lecture 20 |
Nov 28 |
High-Level Compilation |
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Lecture 21 |
Nov 30 |
Hardware/Software Co-Design |
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Lecture 22 |
Dec 5 |
Power Reduction Techniques for FPGAs |
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Lecture 23 |
Dec 7 |
Emerging Reconfigurable Technologies |
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Lecture 24 |
Dec 12 |
Course Wrap-up |
Other information