ECE 636 Reconfigurable Computing

University of Massachusetts

Welcome to the 636 Course Home Page. This serves as the syllabus for the course. The URL is: http://www.ecs.umass.edu/ece/tessier/courses/636/

Instructor: Russell Tessier, Professor, Department of Electrical and Computer Engineering, tel: 413-545-0160, email: tessier 'at' ecs.umass.edu Office Hours : Mon, Tues 2-3PM

Teaching Assistant: Kekai Hu, email: khu 'at' ecs.umass.edu, Office Hours : Tues 4-5PM, Marston 112

For further information about Reconfigurable computing at UMass, click here


Course Description

Recent advances in VLSI technology have given rise to a new class of computer architectures which take advantage of application-level parallelism. These reconfigurable computers can be quickly customized at the hardware level to perform exactly the computation required in hardware, overcoming the fixed hardware configurations found in many contemporary microprocessors. In this class, we investigate the state-of-the-art in reconfigurable computing both from a hardware and software perspective. The desire to efficiently solve important problems drives reconfigurable computing. Consequently, throughout this class we will discuss several numeric and signal processing applications and the characteristics that make them attractive to reconfigurable computing platforms. Initially, we review in detail the basic building blocks of most reconfigurable computers, field-programmable gate arrays (FPGAs). The characteristics of FPGA VLSI architecture such as the organization of device logic and interconnection resources are examined to quantify hardware limitations. These physical limitations are then contrasted with computer-aided design issues such as the selection of circuit component locations in devices (the placement problem) and subsequent circuit interconnection between components (the routing problem). While discrete FPGA devices offer an abundance of usable logic, most current reconfigurable computing applications require hardware configurations of multiple FPGAs and memory components organized in a computing system. As a final step, we focus on the architecture for existing multi-FPGA systems and on compilation techniques for mapping applications described in a hardware description language to reconfigurable hardware. Specific contemporary reconfigurable computing systems are examined to identify existing system limitations and to highlight opportunities for research. (3 credits)

Prerequisites: Courses ECE353 (Computer Systems Laboratory I) and ECE232 (Hardware Organization and Design) are prerequisites for this class. Experience in ECE558 (Intro to VLSI Design) and ECE568 (Computer Architecture) may be helpful in understanding some of the course material but are not required. UMass undergraduates may take this course with the instructor's permission.

Grading: Homework (15%), Final Project (25%), Mid-Term (25%), Class participation/effort (5%), Final Exam (30%)

Honesty Policy: Consultation with fellow students is encouraged, especially on design issues. However, directly copying another student's work defeats the purpose of the assignments and is an honor code violation. All written assignments should be original work. Portions of written work that are taken word-for-word from other authors (students or researchers) will be assigned a failing grade and may result in a failing grade in the course.

Computer Requirements: On-campus students will be doing labs using CAD software on UNIX workstations and PCs.

Course text (optional): Reconfigurable Computing, Scott Hauck and Andre DeHon, Morgan Kaufmann, 2008, ISBN: 978-0-12-370522-8

Reference Material: Research papers will be suggested reading for each class to help stimulate discussion. Birth and Adolescence of Reconfigurable Computing: A Survey of the First 20 Years of Field-Programmable Custom Computing Machines by Pocek, Tessier and DeHon, Reconfigurable Computing and Digital Signal Processing by Tessier and Burleson, and FPGA Architecture: Survey and Challenges by I. Kuon, et al. provide a good introduction to reconfigurable systems.

Homeworks : There will be three homework assignments that involve the development and use of CAD tools for reconfigurable computing including VPR, an academic FPGA place and route system.

Problem Set 1  Problem Set 2 Problem Set 3

Course Project : This page provides information regarding the course project.

Course Philosophy : My goal is for students to become familiar with the state-of-the-art in reconfigurable computing. During the course open research problems in the field will be noted and students will have the opportunity to begin preliminary investigation of these issues through classroom projects.


Schedule (this WILL change throughout the semester )
 

Event 

Fall 13

Topics

Notes

Reading 

Lecture 1

Sep 3

Introduction, Objectives, Expectations, Logistics 

(ppt) (pdf)

Mangione-Smith paper , Compton paper

Lecture 2

Sep 5

Field Programmable Gate Arrays I

(ppt) (pdf)

Betz paper, Lewis paper

Lecture 3

Sep 10

Field Programmable Gate Arrays II

(ppt) (pdf)

Ahmed paper, Lemieux paper

Lecture 4

Sep 12

FPGA Placement

(ppt) (pdf)

Marquardt paper, Tessier PhD, chapter 4

Lecture 5

Sep 17

FPGA Routing

(ppt) (pdf)

Swartz paper, VPR paper

Lecture 6

Sep 24

Network Virtualization with FPGAs

(ppt) (pdf)

Yin paper, Unnikrishnan paper

Lecture 7

Sep 26

On-chip Monitoring Infrastructures

(ppt) (pdf)

GLVLSI12 paper, Zhao paper

Lecture 8

Oct 1

Dynamically Reconfigurable Adaptive Viterbi Decoder

(ppt) (pdf)

Adaptive Viterbi paper, TVLSI AVA paper

Lecture 9

Oct 3

Multi-FPGA Partitioning

(ppt) (pdf)

Bipartition paper , Multicore paper

Lecture 10

Oct 8

Logic Emulation

(ppt) (pdf)

Virtual wires TCAD paper , DEEP paper

Lecture 11

Oct 10

Reconfigurable Computing Applications

(ppt) (pdf)

Lockwood paper , Wrighton paper

Lecture 12

Oct 17

High Level Compilation

(ppt) (pdf)

Parallelizing silicon paper , Goldstein paper

Lecture 13

Oct 22

Exam 1 Review

(ppt) (pdf)

Path delay paper (not covered on exam)

 

Oct 24

Exam 1

 

FPGA high level synthesis paper (not covered on exam)

Lecture 14

Oct 25

VLSI/FPGA Design for Wireless Communication Systems

Prof. Huang (WPI)

 

Lecture 15

Oct 31

Reconfigurable Coprocessors

(ppt) (pdf)

Chimaera paper, Garp paper

Lecture 16

Nov 5

Power Reduction Techniques for FPGAs

(ppt) (pdf)

Anderson paper, Tessier paper

Lecture 17

Nov 7

Reconfigurable Memory Security

(ppt) (pdf)

Vaslin paper, Crenne paper

Lecture 18

Nov 14

Hardware Monitors to Protect Network Processors

(ppt) (pdf)

Chandrikakutty paper, Hu paper

Lecture 19

Nov 19

General Purpose Graphics Processor for FPGAs

K. Andryc (UMass)

Andryc paper

Lecture 20

Nov 21

Exam 2 Review

(ppt) (pdf)

SATA core paper (not covered on exam)

 

Nov 26

Exam 2

 

FPGAs in the cloud (not covered on exam)

Lecture 21

Dec 3

Student Project Presentations I

 

FPGA radar processing (not covered on exam)

Lecture 22

Dec 5

Student Project Presentations II

 

FPGA phase detection (not covered on exam)


Other information


tessier 'at' ecs.umass.edu