This page holds information you need to complete problem set 1 for the course.
Click here for a pdf version of the problem set 1 description.
The homework assignment can be completed using any computer system you wish although I will only be providing support for the UMass ECS Linux computing facility (e.g. quark.ecs.umass.edu). It is assumed that the student is familiar with basic Unix commands such as ‘tar’ and ‘gzip’ and the use of basic makefiles. Please contact the TA (Kekai Hu - email@example.com) if you have specific installation questions.
Please follow the following steps for best results on a generic Unix system (including barney after you have made the changes suggested above):
1. Click here for needed binary, source, and circuit description files. Note: When unzipped this directory will take up about 2 MB.
2. Gunzip (using ‘gunzip ps1.tar.gz’ and ‘tar xvf ps1.tar’) the file to create a directory ps1 and a series of subdirectories.
3. Go to the course Moodle web site and download the source for VPR, version 4.30. Your downloaded file (vpr_430_tar) will also include t-vpack. Do not use other versions of VPR you find on the web for this assignment.
4. Move the file vpr_430_tar into subdirectory ps1/ps1_software
5. Untar the VPR files using ‘tar xvf vpr_430_tar’. Note: This will take up about 3 MB
6. Delete all .o files in ‘trans_count’, ‘t-vpack’, and ‘vpr’ subdirectories and use ‘make’ in each subdirectory to create binaries for your machine
7. You can perform experiments using subdirectories in the ‘tests’ subdirectory.
A reference to help you complete the homework:
D. Lewis, et al, The Stratix II Logic and Routing Architecture, International Symposium on Field Programmable Gate Arrays , February 2005, pdf
I. Kuon and J. Rose, Measuring the Gap Between FPGAs and ASICs, International Symposium on Field Programmable Gate Arrays , February 2006, pdf
A. Marquardt, V. Betz, and J. Rose, Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density, International Symposium on Field Programmable Gate Arrays , February 1999, pdf
Other references were assigned reading for the lectures.