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NASICs (Nanoscale Application Specific ICs and Architectures)
- we are designing circuits and architectures based on carbon nanotubes (CNT) and silicon nanowires (SiNW)
- we have published several papers recently (see our publications for details)
- collaborating with several device physics groups (e.g., Mark Tuominen's group)
Cool-* (read CoolStar) is our flagship research; it is a,
statically speculative, low-power microprocessor architecture.
Our goal is to reduce power and energy consumption by a suite
of combined architecture-compiler techniques. Our main philosophy
is leveraging static information speculatively and providing support
for static execution modes in addition to other circuit and
architecture level techniques. We estimate that our approach can
reduce power (energy) by 40-70% of a state-of-the-art low-power
microprocessor such as the StrongARM. We have developed
techniques in different areas of the processor, the Cool-*
suite, e.g., Cool-Cache (see Micro-34, Dec 2001), Cool-Fetch
(ACM Computer Architecture Letters, 2002, May), Cool-Mem
(to appear in ASPLOS 2002), Cool-Run (in progress),
Cool-Ways(submitted), Cool-Watts (in progress), MiniMax Cache (in HPCA 2002)).
Check the list of publications for already published works and check
back later because we have many interesting approaches cooking in the
pipeline .....
A fully compiler-enabled memory system.
It integrates software cache partitions, compiler managed partitions, and
conventional cache partitions into a uniform memory system framework.
We plan to target FlexCache to:
- synthesize caches for reconfigurable architectures,
- provide predictable memory systems in real-time embedded systems
- improve caching efficiency in microprocessors
- reduce power consumption in memory systems.
- integrating cache coherence with fine grained synchronization in SMP/NUMA/single-chip-multiprocessors
- we have built a multiprocessor simulator that supports synchronization coherence up to 512 nodes
- collaboration with Vlad Vlassov (KTH Stockholm) and Richard Weiss (Hampshire College)
EuphoriaLite focuses on scalable software infrastructure
for global dynamic content management applications on cluster
of workstations and multiprocessors, as well as in distributed
embedded systems. Euphoria implements it's scalable/adaptive
resource management based on:
- non-intrusive introspection byte code level analysis and
transformations (Java and .NET CLR),
- individualized content management,
- object cache store management,
- analytical forecasting models.
- web caching
- wireless client integration HTML/XML-WAP
- real-time JVM for resource constrained devices
From the outside it aims to be compatible with application
server and client software technologies such as defined in J2EE,
J2ME, CLDC, WAP, KVM specifications and have support for both
traditional web based and wireless clients.
Software virtualization techniques
- Hot Pages
- Compiler Managed Memory
Analytical and Compiler Generated Simulation of Billion Transistor
Architectures (back to top)
- Integrated framework for cost performance
valuation of architectures with 1000s of processing units
- SimpleFit - analytical modeling of Raw and FPGAs
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