System Specification

 

Concept:

The ultra wide band digital wireless link is a radio designed for short range, high data rate, one-way communication.  The main idea is to have a data input into the transmitter; from here it is changed into an ultra wide band signal and sent out through an antenna.  The receiver then collects this signal and changes it back into a digital format, and will be available for use.  The signal being transferred runs at a frequency of 600MHz to 2000MHz, and has a data rate of approximately 100 kb/s.  The design is a scaled proof of concept; ideally the frequencies would run between 3MHz and 10MHz, with a much faster data rate.

Inputs/Outputs and System Block Diagram

There are five inputs into the ultra wide band (UWB) system.  The first is a clock, which runs at a frequency of 1 MHz, and is used to run the PLDs.  Ground and a voltage of 2-5 volts are connected to power both the transmitter and receiver block.  There is a mode select input on both sides of the system as well.  This mode select bit is used to choose whether the system will send and receive one byte at a time, or continuous data.  These features are exceptionally helpful for debugging purposes.  The final input is the data that is sent into the transmitter.  The size of this data will vary.

The main output of this system is the data that has been converted back from UWB to digital format on the receiver end of the system.  The size of this output will vary depending on the mode select input.  A RX-flag bit is also sent out of the receiver.  The bit indicates the current state of the receiver, if high then the receiver buffer is full and if low it is not.  A similar bit known as the TX-flag is on the transmitter.  This flag however is high when the buffer is full and no more data can be sent at that time, and is low when it is ready to accept data to send.

System Block Diagram

Specifications of the Blocks

Transmitter

PLD

This block acts as the control unit for the transmitter.  It takes in the data input, a clock, and a mode select bit.  When the mode select bit is low the receiver will be set up to send one byte at a time, and when it is high it will send a continuous stream of buffered data.  The output is the clock, the data, and the TX-flag.  The TX-flag is high when the PLD can no longer take in data from the user because the buffer is full, and is low when it is able to.

Pulser

This block takes in a one kilohertz square wave, and outputs pulses with a rise time in magnitude of hundreds of picoseconds.

Low Pass Filter (LPF)

The LPF has a cutoff of approximately 10kHz.  It takes a square coming out of the PLD and changes it into a cosine.

Mixers

There are two of these blocks.  One takes in the output of the pulser and some logic (in this case it is our data amplified).  This then outputs pulse-modulated data.  The second takes in the output of the pulser and a cosine from the LPF. This results in a pulse modulated cosine.

Summation

This block takes in two pulse-modulated signals, one from each mixer, adds them together and sends its data to the antenna.

Antenna

The antenna takes the final ultra wide band signal and broadcasts it out to the receiver.

Receiver

Antenna

The antenna takes in the ultra wide band signal and makes it available to necessary components.

 

Mixers

There are two of these blocks in the receiver.  The both take in the signal being received by the antenna; one also takes in a cosine from the LPF.  This mixer then outputs its value to the second mixer, which then provides the data to the integrator.  The two mixers and the antenna combined act as a square-law device.

 

Low Pass Filter

The LPF has a cutoff of approximately 10kHz.  It takes a square coming out of the PLD and changes it into a cosine.

 

Integrator

This block takes in the value in which to integrate the ultra wide band signal by, and outputs this integration value.  It is used to change the ultra wide band into a signal that can later be changed to a digital value by the PLD.

 

PLD

This block acts as the control unit for the receiver.  This takes in a clock, a mode select bit, and the values from the integrator, LPF, and antenna.  The mode select bit is identical to the one on the transmitter; high means continuous output, low means receives one byte at a time.  The input from the antenna and LPF is used to determine the phase shift, and this value is sent out to the integrator as the value for τ.  The value then receiver from the integrator is used to create the digital data output.  The PLD samples these values coming from the integrator and sums all the values for time τ.  If the value of this summation is negative then it is equal to a one and if it equals a positive value it is equal to a zero. 

Description of the System

The PLD on the transmitter takes in the data and select bits and then outputs the clock and data.  The clock is sent to the low pass filter so that a cosine is formed.  At the same time the pulser is producing pulses with nanosecond rise times from a one kilohertz square wave.  The data and pulses are then combined in the mixer.  Another mixer is combining the cosine from the LPF with the pulses.  These two mixes are then summed to create an ultra wide band signal that is sent out through the antenna.

On the receiver end the data is taken in by the antenna and put through a square-law device.  A square-law device takes a signal squares it, and modulates it with a cosine.  This cosine is coming from the PLD as it passes through a low pass filter.  As the LPF outputs this cosine wave the PLD analyzes it to find the phase.    Once the phase has been determined the value is sent to the integrator.  At this point the data received that has now been squared and cosine modulated is integrated to extract the useful data information.  The PLD then takes this useful information and coverts it back to the data format that was originally sent from the transmitter.