RAMP: Reliability Model
Cool-Fetch is an architecture-compiler based approach to reduce total energy consumption of wide-issue superscalar processors running typical workloads. While we mainly targeted the fetch unit, an important side-effect of our approach is that we obtained energy savings in many other parts in the processor. The explanation is that the fetch unit often runs substantially ahead of execution, bringing in instructions to different stages in the processor that may never be executed. We have found, that although the degree of Instruction Level Parallelism (ILP) of a program tends to vary over time, it can be statically predicted by the compiler with considerable accuracy. We developed an Instructions Per Clock (IPC) prediction scheme which used a dependence-testing-based analysis and simple heuristics, to guide a front-end fetch-throttling mechanism.
We developed the necessary architecture support and included its power overhead. We performed experiments over a wide number of architectural configurations, using SPEC2000 applications. Our results were very encouraging: we obtained up to 15% total energy savings in the processor with generally little performance degradation. In fact, in some cases our intelligent throttling scheme even increased performance. The following figure shows percentage energy savings for various processor blocks and performance degradation/increase (decrease in IPC) for SPEC2000 applications.