ECE 793 SEMINAR
Rensselaer Polytechnic Institute
Where: Marston 132
As CMOS technology is scaling down to sub-100nm regime, process and environmental variations have become one of the most crucial design challenges and may significantly jeopardize today and future integrated circuits (IC) energy and silicon area efficiency. Meanwhile, efficient signal processing IC implementations are of critical importance in the pervasive communication and computing era because of their ubiquity and significant impact on overall system energy and silicon cost. Certain unique features shared by most signal processing algorithms, together with the importance of efficient signal processing IC implementations, justify a domain-specific investigation on algorithm-based variation tolerance techni
ques for signal processing functions. Intuitively, the effectiveness of such domain-specific variation tolerance can be maximized by vertically integrating algorithm/architecture with physical level implementation. In this talk, we will present our recent work on pursuing cross-layer variation-tolerant signal processing system design methods. Motivated by the fact that variation-induced errors on different circuit logic signals may have largely different effects on the overall performance, we proposed an algorithm-based performance-centric unequal variation tolerance design framework, which is conceptually similar to the unequal error protection techniques being widely used in wireless image/video transmission. We will demonstrate its effectiveness using a case study on trellis decoders, which are being widely used in digital communication.