ECE 793 SEMINAR

Thermal Design and Gate Sizing for FinFETs

(Required for Computer Systems Area Graduate Students)

Soha Hassoun
Tufts University
Department of Computer Science
http://www.cs.tufts.edu/~soha/


Where: Marston 132

When: Friday, Oct. 27, 2006, at 4:00 pm

Abstract

As device dimensions shrink into the nanometer range, power and performance demands prohibit the longevity of traditional MOS devices in circuit design. A finFET, a quasi-planar double-gated device, has emerged as a replacement. A finFET is formed by creating a silicon fin which protrudes out of the wafer, wrapping a gate around the fin, and then doping the ends of the fin to form the source and drain. We present in this talk an overview of finFETs, focusing on thermal device design and gate sizing issues. While finFETs provide promising electrostatic characteristics, they, like other ultra-thin body nano devices, have the potential to suffer from significant self heating. We propose a distributed thermal channel model use it to study the electro-thermal properties of multi-fin devices with both flared and rectangular channel extensions. We analyze variations in fin geometric parameters such as fin width and gate length, and we investigate the impact on thermal sensitivity using our thermal sensitivity metric, METS. We also report on gate sizing and independent gate biasing of finFET circuits. We show that finFET circuits are superior to 32nm circuits in performance, and in both dynamic and static power consumption.


Speaker Bio:

Soha Hassoun is currently an associate professor at Tufts University in the Department of Computer Science. She earned an MS in Electrical Engineering from MIT, and a Ph.D. from the Computer Science and Engineering Department at the University of Washington, Seattle. Dr. Hassoun's research interests include CAD, VLSI design, and computer architecture. Prior to pursuing her Ph.D., Dr. Hassoun worked as a chip designer in the microprocessor design group at Digital Equipment Corporation. She was one of the 21064 Alpha processor's circuit designers. She also designed a commercial cache controller for the VAX 6400, a vector processor, a 3-transistor dynamic RAM at MIT, and a router chip at UW. She spent January-July 2002 at IBM research labs in Austin. Dr. Hassoun served as the technical program chair for ICCAD 2005, and currently serves as the general chair. She has served on several other program committees. She is the founder of the PhD forum at DAC, and SIGDA Design Automation Summer School, and the CADathlon programming contest at ICCAD.