ECE 793 SEMINAR
Department of Computer Science
Where: Marston 132
As device dimensions shrink into the nanometer range, power and
performance demands prohibit the longevity of traditional MOS devices
in circuit design. A finFET, a quasi-planar double-gated device, has
emerged as a replacement. A finFET is formed by creating a silicon
fin which protrudes out of the wafer, wrapping a gate around the fin,
and then doping the ends of the fin to form the source and drain.
We present in this talk an overview of finFETs, focusing on thermal
device design and gate sizing issues. While finFETs provide promising
electrostatic characteristics, they, like other ultra-thin body nano
devices, have the potential to suffer from significant self heating.
We propose a distributed thermal channel model use it to study the
electro-thermal properties of multi-fin devices with both flared and
rectangular channel extensions. We analyze variations in fin
geometric parameters such as fin width and gate length, and we
investigate the impact on thermal sensitivity using our thermal
sensitivity metric, METS. We also report on gate sizing and
independent gate biasing of finFET circuits. We show that finFET
circuits are superior to 32nm circuits in performance, and in both
dynamic and static power consumption.