ECE 793 SEMINAR

A VLSI Systolic Architecture for Neural Networks Trained by Error-backpropagation

Alodeep Sanyal
University of Massachusetts, Amherst
Department of Electrical & Computer Engineering

Abstract: 

Back propagation, a well known technique in artificial neural networks, is computation intensive, and offers the scope to exploit a high degree of parallelism. We present implementation of a one-dimensional linear systolic array for the entire learning phase of the back propagation algorithm, after which the architecture passes directly into the application phase. For a neural network with P input neurons, Q hidden layer neurons and R output neurons, this new architecture with Q processors, exhibits a running time of (2P+R+max(Q,R)) per training instance. The architecture reports better running time and, therefore, an improvement over the most efficient hardware solution reported in literature to date.
We describe the back propagation algorithm using a very high level language (ALPHA) and perform design exploration with an automatic systolic array synthesis tool, called MMALPHA, to generate the RTL description of this architecture. We use a Field Programmable Gate Array (FPGA) coprocessor as the hardware implementation medium. We report the performance of the proposed architecture when applied to two real applications, viz. i> the exclusive-or problem; and ii> the cart-pole balancing problem. We report an operating frequency of 45 MHz (highest reported in literature to date) and a sustained throughput of 3.6 Giga Operations Per Seconds (GOPS) for our proposed architecture when implemented on a Xilinx Virtex-II FPGA, XC2V6000.


Speaker Bio:

Alodeep Sanyal is currently a Doctoral student in the Department of Electrical and Computer Engineering of University of Massachusetts at Amherst. He obtained his Bachelor of Technology in Electronics and Communications Engineering from University of Kalyani, India in 2002, and Master of Science in Computer Science from Colorado State University, USA in 2005. Alodeep has published two conference papers and a referred journal paper till date in the fields of VLSI testing, genetic algorithms, and solid state semiconductor devices and superconductive materials. The talk is based on his MS Thesis which he defended in August 2005.