ECE 793 SEMINAR
Where: Marston 132
State-of-the-art high-performance digital ICs manufactured in deep-submicron technologies tend to draw considerable amounts of power during operation. Large transients, i.e., sharp changes in power consumption, are possible within a few clock cycles. These changes are known as power droop and are instances of power supply noise. Although power droop may induce a delay fault which causes an IC to fail, such failures cannot currently be screened during testing as they are not covered by conventional fault models.
The presentation will focus on generation of specific test sequences which are required to screen ICs for power droop. The sequences can be used for manufacturing testing as well as for early silicon validation. The generated patterns need to be sequential even for scan designs.
First, the physics of power droop and its implications on logic signal integrity will be briefly sketched. Low-frequency and high-frequency components of power droop will be described. Then, the test generation flow will be presented. Test sequences must satisfy a variety of conditions in order to maximize both low-frequency and high-frequency power droop and combine their effects. Such sequences are obtained by a dynamically constrained version of the classical D-algorithm for test generation, i.e., the algorithm generates new constraints on-the-fly depending on previous assignments. Finally, first results, which have been produced by a prototype automatic test pattern generator implemented to demonstrate the feasibility of the approach, will be discussed.