Vhdl

Use sold for official help

Online general vhdl language references:

http://www.cs.umbc.edu/help/VHDL/index.shtml/

http://www.devry-phx.edu/fac/miller/vhdl_index.htm/

Very simple example: Nor Gate. This example is designed to introduce you to the Synopsys^TM version of Vhdl, not to be a demonstration of how to code in Vhdl.

Suppose you want to simulate the following vhdl code. You will need to learn the constructs of vhdl on you own. The links above will be very helpful.

/* Nor Gate Example: nor.vhdl/

library IEEE;

use IEEE.std_logic_1164.all;

entity N_O_R is

port (a : in std_logic;

b: in std_logic;

c: out std_logic);

end N_O_R;

architecture logic of N_O_R is

begin

c <= a nor b;

end architecture logic;

1. First you must generate a stimulus module. This module can be put in the same file as the original code but I prefer to separate the stimulus. This will allow you to use the original code as a subsystem in a larger design. The following is a simple stimulus file.

/* nor gate test stim.vhdl */

library IEEE;

use IEEE.std_logic_1164.all;

entity test is

end;

architecture A of test is

component N_O_R is

port (A,B: in STD_LOGIC;

C : OUT STD_LOGIC);

end component;

signal A: STD_LOGIC :='0';

signal B: STD_LOGIC :='0';

signal C : STD_LOGIC;

begin

---Instantiate the N_O_R model

N_O_R1: N_O_R port map(A,B,C);

---The waveform that drives the adder follows

DRIVER: process

begin

wait for 5 ns;

A <= '1'; --five time units later A changes to 1

wait for 5 ns;

A <= '0';

B <= '1';

wait for 5 ns;

A <= '1';

wait;

end process;

end;

configuration Ctest of test is

for A

for all : N_O_R

use entity WORK.N_O_R(logic);

end for;

end Ctest;

2. The next step is creating a simple file which lists all the signals interested for a given simulation. Followed by expected simulation time.

/*Configuration file for a 2 input nor gate, sim.inc */

trace A

trace B

trace C

run 50

3. Once the files (nor.vhdl, stim.vhdl, sim.inc) are created the vhdl simulator from Synopsys can be invoked from the command line.

example> vhdlan nor.vhdl stim.vhdl

This results in the following terminal output(if no error):

Synopsys 1076 VHDL Analyzer Version 2000.06 -- May 24, 2000

This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure

4.input the following command to invoke the debugger and simulation waveform

example>vhdldbx

5. In the window that comes up, type -i sim.inc in the arguments box before hit OK button .

6. A Synopsys Vhdl Debugger window will come right away, however, for the first time use, it takes a while to generate fonts..

7. Automatically,Synopsys Waveform Viewer will appear.