ABC is the state-of-the-art academic tool for logic synthesis and verification - both combinational and sequential. Detailed information about ABC is provided at the main ABC website, which also provides links to download the source code for linux and windows OS.
Alternatively, you can download it directly from https://bitbucket.org/alanmi/abc
Here is the binary version for Windows: abc80916.exe
Input to ABC is represented in BLIF format.
(Berkeley Logic Interchange Format).
For a simple circuit, the easiest way to create a file in blif format
is to first write Boolean expressions of the circuit in a simple equation format, eqn (see example below), read it using ABC, and write out the blif version. ABC can also read and write out structural verilog file.
You can then generate a blif or file using ABC as follows:
The following link contains a simple ABC demo for combinational synthesis, including mapping into standard cells and LUTs.
Sequential circuits can be similarly obtained represented in blif format. The following example shows how to generate a sequential blif for a simple finite state machine (FSM): fsm-example
In your work you will need a standard cell library, such as
These are simple text files to be read-in with a read_library command. The format of the genlib library is explained in the genlib-format.pdf document.For mapping onto FPGAs, you will need a LUT-based library:
to be read-in with a read_lut command. The format of that file is self explanatory, explained with comments in the lib file.The result of your synthesis work (a mapped netlist) can be written into a verilog file, using the following abc command: