Current Lectures

INTRODUCTION

HIGH-LEVEL SYNTHESIS

LOGIC SYNTHESIS Spring recess (March 14-18)

Midterm Exam : March 23, at 7:00 pm, ELAB 323.

  • Lecture 15. March 24 - Multi-level synthesis: Kernel-based optimization.
    Reading material: DeMicheli, Sections 8.3; Hachtel/Somenzi, Chapter 10.

  • Lecture 16. March 29 - Technology mapping (ASIC): Tree-based mapping.
    Reading material: DeMicheli, Section 2.3, Chapter 10; and Hachtel/Somenzi, Chapter 13.

  • Lecture 17. March 31 - Technology mapping, cont'd.

    STUDENT PRESENTATIONS

    April 05, 07, 12, 14, 21 and 23. Consult the following Presentation schedule (with copies of the presentation slides).
    NOTE: there is a regular class on April 19th, see below.

  • Lecture 21. April 19 - Sequential logic optimization: Retiming.
    Reading material: DeMicheli, 9.3
    Review of Dijkstra and Bellman-Ford Shortest Path algorithms.

    VERIFICATION

  • Lecture 24. April 26 - Formal verification: Verification basics; Combinational Equivalence Checking.

  • Lecture 25. April 28 Formal verification: Scalable Sequential Verification with ABC, presented by Alan Mishchenko.

  • Lecture 26. May 03 Formal verification, cont'd. Sequential Equivalence Checking. Course conclusion.

    Final exam - Thursday, May 5th, at 8:00 am in Marston 211. Come prepared!