ECE 667 - Synthesis and Verification of Digital Systems
Spring 2011
Homework Assignments

Homework #1, due Feb. 22
Use the following link to learn about different LP Solvers and LP problem formulation.
Homework #2, due March 10.
Homework #3, due March 31.
Please work on the first two problems (BDDs) to prepare for the midterm exam.
Homework #4, due April 14.
You will need the following files for this homework:
- Verilog file: prefix-adder.v
- Verilog file: ripple-adder.v
- Standard cell library: stdcell.lib
- FPGA library: fpga.lib
Homework #5, due: extended to May 05 at the exam (8:00 am).