Office hours: Mon., Wed. 2:00 - 3:00 or by appointment
ciesiel@ecs.umass.edu
There will be five homework assignments, one midterm exam
(testing your knowledge of theory) and the final exam.
Homework assignments will include the use of synthesis tools, such as
GAUT, ABC, BDS, TDS, and commercial tools, available on CSE Unix servers.
The final grade will be determined as follows:
Additional references.
Course Information
The first part of the course covers basic techniques of high-level and
architectural synthesis, including operation scheduling, resource allocation
and binding.
Next, the fundamentals of Boolean algebra, logic function representations,
and basic logic optimization algorithms are introduced.
We shall concentrate on those parts of the theory that will help you
understand how logic synthesis and verification CAD tools work.
This is useful to those who want to develop such tools and to those
who simply want to use them proficiently.
The next part will be devoted to logic synthesis, concentrating mostly
on multi-level synthesis and technology mapping.
Application to both ASICs and FPGAs will be discussed.
The last part will cover Verification, with emphasis on formal methods (equivalence checking and model checking) and satisfiability.
Grading
NO INCOMPLETE grades will be allowed, so please plan accordingly.
Textbook
In addition, students will be given a set of handouts and research papers.
Errata
Prerequisites: