ECE 667 - Synthesis and Verification of Digital Systems
Spring 2011
Exam schedule
Midterm Exam: Wednesday, March 22, at 7:00 pm, ELAB 323.
The exam is 2-hour long, closed books, close notes, open minds.
It covers the following material:
- High-level synthesis, algorithms for scheduling and allocation.
- Two-level logic synthesis: basic theory;
exact logic synthesis algorithms (Quine); and heuristic methods (espresso).
- BDDs: construction, theory, manipulation (APPLY algorithm), application.
Final Exam: Thursday, May 05, at 08:00 am, Marston 211
The exam is two-hour long, closed books, close notes, open minds.
It covers the second part of the course, including:
- Multilevel logic synthesis
- Retiming
- SAT, CNF-based
- Sequential verification: equivalence checking, FSM traversal
- Topics covered by student presentations: FPGA mapping, BMDs, SMT (basics)