Accurate Estimation of Soft Error Rate (SER) in VLSI Circuits

Proc. of the International Symposium on Defect and Fault Tolerance in VLSI Systems, (DFT'04), 2004.

A. Maheshwari, I. Koren and W. Burleson

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Abstract

(Complete manuscript in pdf format).


Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits

Proc. of the International Symposium on Defect and Fault Tolerance in VLSI Systems, (DFT'03), 2003.

A. Maheshwari, I. Koren and W. Burleson

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Abstract

(Complete manuscript in pdf format).


Incorporating Fault Tolerance in Analog-to-Digital Converters (ADCs)

Proc. of the International Symposium on Quality of Electronic Design (ISQED'02), 2002.

M. Singh and I. Koren

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Abstract

The reliability of ADCs used in highly critical systems can be increased by applying a two-step procedure starting with sensitivity analysis followed by redesign. The sensitivity analysis is used to identify the most sensitive blocks which could then be redesigned for better reliability by incorporating fault tolerance. This paper illustrates the steps involved in incorporating fault tolerance in an ADC. Two redesign techniques to improve the reliability of a circuit are presented. Novel selective node resizing algorithms for increased tolerance against alpha-particle induced transients are discussed.

(Complete manuscript in Postscript format). (or PDF format).


Reliability Enhancement Techniques for Analog-to-Digital Converters (ADCs)

Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2001.

M. Singh and I. Koren

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Abstract

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. The reliability of these systems is affected by the ability of its constituent blocks to tolerate faults. Therefore, it is necessary to increase the reliability of ADCs to ensure a highly reliable critical system. This paper illustrates the steps involved in the reliability enhancement of ADCs by first proposing a methodology for fault sensitivity analysis and then illustrating redesign techniques to improve the reliability of the highly sensitive(to faults) blocks.

(Complete manuscript in PostScript format).


Advanced Fault-Tolerance Techniques For A Color Digital Camera-On-A-Chip

Proc. of the 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

I. Koren, G. Chapman and Z. Koren

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Abstract

Color digital imagers contain Red, Green and Blue subpixels within each color pixel. Defects that develop either at fabrication time or due to environmentally induced errors over time can cause a single color subpixel (e.g., R) to fail, while leaving the remaining colors intact. This paper investigates seven software correction algorithms that interpolate the color of a pixel based on its nearest neighbors. Using several measurements of color error, all seven methods were investigated for a large number of digital images. Interpolations using only information from the single failed color (e.g., R) in the neighbors gave the poorest results. Those using all color measurements and a quadratic interpolation formula, combined with the remaining subpixel colors (e.g., G and B) produced significantly better results. A formula developed using the CIE color coordinates of Tristimulus values (X, Y, Z) yielded the best results.

(Complete manuscript in PostScript format).


Transient Fault Sensitivity Analysis of Analog-to-Digital Converters

Proc. of WVLSI 2001.

M. Singh, R. Rachala and I. Koren

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Abstract

Reliability of systems used in space, avionic and biomedical applications is highly critical. Such systems consist of an analog front-end to collect data, an ADC to convert the collected data to digital form and a digital unit to process it. It is important to analyze the fault sensitivities of each of these to effectively gauge and improve the reliability of the system. This paper addresses the issue of fault sensitivity of ADCs. A generic methodology for analyzing the fault sensitivity of ADCs is presented. A novel concept of ``node weights" specific to alpha-particle induced transient faults is introduced to increase the accuracy of such an analysis.

(Complete manuscript in PostScript format).


A Self-Correcting Active Pixel Camera

Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

I. Koren, G. Chapman and Z. Koren

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Abstract

Digital cameras on-a-chip are becoming more common and are expected to be used in many industrial and consumer products. With the size of the CMOS active pixel-array implemented in such chips increasing to 512 x 512 and beyond, the possibility of degradation in the reliability of the chip over time must be a factor in the chip design. In digital circuits, a commonly used technique for reliability or yield enhancement is the incorporation of redundancy (e.g., adding redundant rows and columns in large memory ICs). Very limited attempts have been directed towards fault-tolerance in analog circuits, mainly due to the very high level of irregularity in their design. Since active pixel arrays have a regular structure, they are amenable to reliability enhancement through a limited amount of added redundancy. The purpose of this paper is to investigate the advantages of incorporating some fault-tolerance methods, including redundancy, into the design of an active pixel sensor array.

(Complete manuscript in PostScript format).


Three Layer Routing for Reliability Enhancement

Journal of Microelectronic Systems Integration, 1997.

Z. Chen and I. Koren

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Abstract

In this paper we study two important reliability issues in deep submicron VLSI design, namely antenna effect and crosstalk noise, in the context of three-layer channel routing. Cost functions for both of the failure mechanisms are introduced and based on these cost models, reliability enhancement techniques are presented. For antenna effect minimization, a layer reassignment algorithm is adopted while for crosstalk minimization, an algorithm that combines layer reassignment and track reassignment is presented. Experimental results show that these algorithms can reduce the antenna effect and the crosstalk noise considerably without increasing the routing area. The relationship between these two objectives has also been studied and a technique for optimizing them simultaneously is proposed.

The complete paper in postscript (compressed). .


Crosstalk Minimization in Three-Layer HVH Channel Routing

Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 38-42, Oct. 1997

Z. Chen and I. Koren

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Abstract

Crosstalk has become a major issue in VLSI design due to the high frequency, long interconnecting lines and small spacing between interconnects in today's integrated circuits. In this paper, we study the problem of crosstalk minimization in 3-layer HVH channel routing. A heuristic algorithm that combines layer reassignment and track reassignment is presented. This algorithm can iteratively modify the layout so that the crosstalk in the channel is minimized. Experimental results show that the proposed approach can reduce the crosstalk by an average of 16.4% on a set of benchmark examples.


Technology Mapping for Hot-Carrier Reliability Enhancement,

Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97, pp. 42-50, October 1997.

Z. Chen and I. Koren

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Abstract

As semiconductor devices enter the deep sub-micron era, reliability has become a major issue and challenge in VLSI design. Among all the failure mechanisms, hot-carrier effect is one of those which have the most significant impact on the long-term reliability of high-density VLSI circuits. In this paper, we address the problem of minimizing hot-carrier effect during the technology mapping stage of VLSI logic synthesis. We first present a logic-level hot-carrier model, and then, based on this model, we propose a technology mapping algorithm for hot-carrier effect minimization. The proposed algorithm has been implemented in the framework of the Berkeley logic optimization package SIS. Our results show that an average of 29.1% decrease in hot-carrier effect can be achieved by carefully choosing logic gates from cell libraries to implement given logic functions for a set of benchmarks. It has also been observed that the best design for hot-carrier effect minimization does not necessarily coincide with the best design for low power, which has long been considered as a rough measure for VLSI reliability.


Layer Reassignment for Antenna Effect Minimization in 3-Layer Channel Routing

Proc. of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 77-85, Nov. 1996

Z. Chen and I. Koren

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Abstract

As semiconductor technology enters the deep submicron era, reliability has become a major challenge in the design and manufacturing of next generation VLSI circuits. In this paper we focus on one reliability issue - the antenna effect in the context of 3-layer channel routing. We first present an antenna effect model in 3-layer channel routing and, based on this, an antenna effect cost function is proposed. A layer reassignment approach is adopted to minimize this cost function and we show that the layer reassignment problem can be formulated as a network bipartitioning problem. Experimental results show that the antenna effect can be reduced considerably by applying the proposed technique. Compared with previous work, one advantage of our approach is that no extra channel area is required for antenna effect minimization. We show that layer reassignment technique can be used in yield-related critical area minimization in 3-layer channel routing as well. The trade-off between these two objectives is also presented.


The Effect of Spot Defects on the Parametric Yield of Long Interconnection Lines

Proc. of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 46-54, November 1995.

I. A. Wagner and I. Koren

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Abstract

The effect of non-catastrophic (or soft) defects (i.e., neither short nor open) on long interconnection lines is analyzed and an estimate is derived for the frequency-dependent critical area for such lines. The analysis is based on a transmission-line model of interconnection lines, and the reflections caused by the defect are taken into account. This analysis results in an estimated prediction of the parametric yield, and a practical recommendation for a better jog insertion in VLSI routing.

Complete manuscript in PDF format.


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