Constructive Floorplanning with a Yield Objective

Proc. of the 2001 International Symposium on Quality of Electronic Design

R. K. Prasad and I. Koren

Abstract

The ability to improve the yield of integrated circuits through layout modification has been recognized, and several techniques for yield enhanced routing and compaction have been developed. Still, yield issues are rarely a factor in the choice of the floorplan mainly due to the tendency to focus on the more important timing and area objectives. Consequently, floorplanning tools have been developed with only these primary objectives in mind. We show in this paper that it is possible to generate a better floorplan with respect to yield, with very little penalty in the main objectives. We describe a constructive floorplanning approach which is based on analytical techniques and produces near optimal floorplans in terms of area utilization, wiring length and yield.

The complete paper in postscript. .

The Effect of Placement on Yield for Standard Cell Designs

Proc. of the 2000 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

R. K. Prasad and I. Koren

Abstract

The ability to improve the yield of integrated circuits through layout modification has been recognized and several techniques for yield enhanced routing and compaction have been developed. Yield improvement during routing is however, limited by the predetermined placement. It is conceivable therefore, that different placements of the modules (e.g., standard or custom cells) may lead to very different yield enhanced routings with different projected yields. This is conceptually similar to the effect that the floorplanning of the entire chip has on the yield \cite{p2}, but while chip floorplanning deals with the major building blocks, placement deals with the modules within an individual block. Yield enhanced placement of modules has not been attempted before mainly due to the difficulty of estimating the yield of the block before the routing is done. Recently, a technique for estimating the yield prior to the routing has been developed making it possible to modify the placement in order to achieve higher yield. The goals of this paper are to investigate the effect that placement has on the projected yield and to modify a standard cell placement algorithm so that yield becomes a design objective.

The complete paper in postscript. .

Incorporating Yield Enhancement into the Floorplanning Process

IEEE Trans. on Computers, Special Issue on Defect Tolerance in Digital Systems, Vol. 49, June 2000

I. Koren and Z. Koren

Abstract

The traditional goals of the floorplanning process for a new integrated circuit have been minimizing the total chip area and reducing the routing cost, i.e., the total length of the interconnecting wires. Recently, it has been shown that for certain types of chips, the floorplan can affect the yield of the chip as well. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to investigate the two seemingly unrelated, and often conflicting, objectives of yield enhancement and routing complexity minimization. We analyze the possible trade-offs between the two, and then present a constructive algorithm for incorporating the yield enhancement as a secondary objective into the floorplanning process, with the main objective still being the minimization of the overall routing costs.

Index Terms: Floorplanning, microprocessor, memory ICs, redundancy, routing complexity, yield.

The complete paper in postscript. .

Yield and Routing Objectives in Floorplanning

Proc. of the 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

I. Koren and Z. Koren

Abstract

Traditionally the floorplan of a chip has been determined so as to minimize the total chip area and reduce the routing costs. Recently, it has been shown that the floorplan also affects the yield of the chip. Consequently, it becomes desirable to consider the expected yield, in addition to the cost of routing, when selecting a floorplan. The goal of this paper is to study the two seemingly disjoint objectives of yield enhancement and routing complexity minimization, and find out whether they lead to different optimal floorplans, resulting in a need for a tradeoff analysis.

On the Effect of Floorplanning on the Yield of Large Area Integrated Circuits

IEEE Trans. on VLSI Systems, Vol. 5, pp. 3-14, March 1997.

Z. Koren and I. Koren

Abstract

Until recently, VLSI designers rarely considered yield issues when selecting a floorplan for a newly designed chip. This paper demonstrates that for large area VLSI chips, especially those that incorporate some fault tolerance, changes in the floorplan can affect the projected yield. We study several general floorplan structures, make some specific recommendations, and apply them to actual VLSI chips. We conclude that the floorplan of a chip can affect its projected yield in a non-negligible way, for chips with or without fault-tolerance.

Index Terms: Clustering, defects, fault-tolerant ICs, floorplan, large-area ICs, yield.

The complete paper in postscript. .

Layout Synthesis Techniques for Yield Enhancement

IEEE Trans. on Semiconductor Manufacturing, Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 178-187, May 1995.

Venkat K. R. Chiluvuri and Israel Koren

Abstract

Several yield enhancement techniques are proposed for the last two stages of VLSI design, i.e., topological/symbolic and physical layout synthesis. Our approach is based on modifications of the symbolic/physical layout to reduce the sensitivity of the design to random point defects without increasing the area, rather than fault tolerance techniques. A layout compaction algorithm is presented and the yield improvement results of some industrial layout examples are shown. This algorithm has been implemented in a commercial CAD framework. Some routing techniques for wire length and via minimization are presented and the results of wire length reduction in benchmark routing examples are shown. We demonstrate through topological optimization for PLA-based designs that yield enhancement can be applied even at a higher level of design abstraction. Experimental results show that it is possible to achieve significant yield improvements without increasing the layout area by applying the proposed techniques during layout synthesis.

The complete text (not all figures) in postscript (compressed). .

Layer Assignment for Yield Enhancement

Proc. of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 173-180, Nov. 1995

Z. Chen and I. Koren

Abstract

In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness.

Yield Enhancement vs. Performance Improvement in VLSI Circuits

Proc. of ISSM-95, The Intern. Sympos. on Semiconductor Manufacturing, pp. 28-31, Austin, Sept. 1995

V.K.R. Chiluvuri and I. Koren

Abstract

For advanced submicron VLSI technologies maintaining higher performance and better yield is a challenging task. Layout optimization for improving yield may affect the circuit performance and vice versa. We analyze the effect of layout modifications for parasitic capacitance reduction on yield in this paper. Our results show that the solutions to the yield enhancement and parasitic capacitance reduction problems are very close to each other.

Yield Enhanced Routing for High-Performance VLSI Designs

Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97, pp. 50-60, October 1997.

A. Venkataraman, H. Chen and I. Koren

Abstract

It is widely recognized that interconnects will be the main bottleneck in enhancing the performance of future deep sub-micron VLSI designs. Interconnects do not ``scale'' well with decreasing feature sizes and therefore dominate the delays in the integrated circuit. In addition to RC delays, crosstalk noise also contributes significantly to the delays experienced by a signal. Interconnects are more susceptible to manufacturing defects and therefore affect the product yields significantly. Recently, several channel-routing based solutions have been proposed to minimize crosstalk noise and also enhance yield of the routing. While these approaches are effective, they do not provide maximized benefits as they are either constrained by a particular design methodology or are post-routing steps which have very little scope for significant improvement. Also, design for manufacturability objectives have not been fully exploited by VLSI CAD tools as they do not integrate seamlessly into the conventional design flow and the added overheads make it less attractive. In this paper, we propose a modified routing algorithm that maximizes yield and reduces crosstalk noise while using minimal area for the routing. The yield enhancement objective has been integrated into the routing phase as a preferred constraint (a constraint that will be satisfied only if the primary constraints of minimal area and wire length have been satisfied) and fits well into the conventional design flow. This enables the router to produce an output which provides maximum achievable critical area reduction for the given routing solution. Post-routing layout modification is also done with the objective of minimizing the interaction area between the interconnects by exploiting the gridless property of the router. The above algorithm is incorporated into GLITTER (the gridless, variable width channel router), and the results on channel-routing benchmarks are presented. These results show a significant reduction in the critical area achievable by using the proposed algorithm.

Techniques for Yield Enhancement of VLSI Adders

Proceedings of ASAP 95 - the International Conference on Application-Specific Array Processors, pp. 222-229, July 1995.

Z. Chen and I. Koren

Abstract

For VLSI application-specific arrays and other regular VLSI circuits, two techniques are available for yield enhancement, namely defect-tolerance and layout modifications. In this paper, we compare these two yield enhancement approaches by using adders as an example. Our yield projections indicate that the layout modification technique is more efficient when the defect density is low, while reconfiguration is more efficient for a high defect density. However, from the point of the view of effective yield, the layout modification is superior to defect tolerance in the practical range of defect density.

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