UNIVERSITY OF MASSACHUSETTS
Department of Electrical and Computer Engineering

Design for Manufacturability and Reliability of VLSI

References:

( Copyright note )

DFM References (Added in 2007)

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[32]   J. D. Byers, M. D. Smith, and C. A. Mack, “3D lumped parameter model for lithographic simulations,” in Proc. SPIE Vol. 4691, p. 125-137, Optical Microlithography XV, Anthony Yen; Ed., pp. 125–137,July 2002.

[33]   M. D. Smith, J. D. Byers, and C. A. Mack, “Comparison between the process windows calculated with full and simplified resist models,” in Proc. SPIE Vol. 4691, p. 1199-1210, Optical Microlithography XV, Anthony Yen; Ed., pp. 1199–1210, July 2002.

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[40]   S. C. Goldstein, “The impact of the nanoscale on computing systems,” in ICCAD ’05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, (Washington, DC, USA), pp. 655–661, IEEE Computer Society, 2005.

[41]   H. Ren, D. Z. Pan, C. A. Alpert, and P. Villarrubia, “Diffusion based placement migration,” in Proc.Design Automation Conf., 2005.

[42]   T. Luo, H. Ren, C. A. Alpert, and D. Z. Pan, “Computational geometry based placement migration,” in Proc. Int. Conf. on Computer Aided Design, 2005.

[43]   S. N. Adya, I. Markov, and P. Villarrubia, “On whitespace and stability in mixed-size placement and physical synthesis,” in Proc. Int. Conf. on Computer Aided Design, pp. 311–318, 2003.

[44]   C. J. Alpert, G. J. Nam, P. G. Villarrubia, and M. Yildiz, “Placement stability metrics,” in Proc. Asia and South Pacific Design Automation Conf., 2005.

[45]   M. T. Gastner and M. E. J. Newman, “Diffusion-based method for producing density equalizing maps,”Proc. Natl. Acad. Sci. USA, 2004.

[46]   F. Aurenhammer, “Voronoi diagrams: a survey of a fundamental geometric data structure,” ACM Comput.Surv., vol. 23, no. 3, pp. 345–405, 1991.

[47]   H. Ren, D. Z. Pan, C. A. Alpert, and P. Villarrubia, “Diffusion-based placement migration,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 2006 (submitted).

[48]   K. Vorwerk and A. Kennings, “Mixed-size placement via line search,” in ICCAD ’05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, (Washington, DC, USA), pp. 899–904, IEEE Computer Society, 2005.

[49]   S. Zhang andW. Dai, “TEG: A new post-layout optimization method,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, pp. 446–456, Apr. 2003.

[50]   J. Cong and Y. Zhang, “Thermal-driven multilevel routing for 3-d ics,” in ASP-DAC ’05: Proceedings of the 2005 conference on Asia South Pacific design automation, (New York, NY, USA), pp. 121–126, ACM Press, 2005.

[51]   T. Zhang, Y. Zhan, and S. S. Sapatnekar, “Temperature-aware routing in 3D ICs,” in ASP-DAC ’06:Proceedings of the 2006 conference on Asia South Pacific design automation, (New York, NY, USA), pp. 309–314, ACM Press, 2006.

[52]   K. Balakrishnan, V. Nanda, S. Easwar, and S. K. Lim, “Wire congestion and thermal aware 3D global placement,” in ASP-DAC ’05: Proceedings of the 2005 conference on Asia South Pacific design automation, (New York, NY, USA), pp. 1131–1134, ACM Press, 2005.

 

Created by Prof. Israel Koren, koren at ecs.umass.edu