Department of Electrical and Computer Engineering

**
Design for Manufacturability and Reliability of VLSI
**

__DFM References (Added in 2007)__

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- Background (Yield ... or else!):
- EBT 10/97: Semiconductor Report
- F. Schellenberg, “A little light magic,”
*IEEE Spectrum*, Sept. 2003.

- Books (Yield and Reliability):
- J. P. de Gyvez
*et al.*(ed.),*Integrated Circuit Manufacturability: The Art of Process and Design Integration,*IEEE Press, 1999. - B. Ciciani (editor),
*Manufacturing Yield Evaluation of VLSI/WSI Systems,*IEEE Computer Society Press, Los Alamitos, California, 1998. - A.V. Ferris-Prabhu,
*Introduction to Semiconductor Device Yield Modeling,*Artech House, 1992. - J. P. Gyvez,
*Integrated Circuit Defect-Sensitivity: Theory and Computational Models*, Kluwer Academic Publishers, Boston, 1993. - S.W. Director, W. Maly and A.J. Strojwas,
*VLSI Design for Manufacturing: Yield Enhancement,*Kluwer Academic Publishers, Boston, 1990. - D.M.H. Walker,
*Yield Simulation for Integrated Circuits*, Kluwer Academic Publishers, Boston, 1987. - Y.-K. Cheng, C.-H. Tsai, C.-C. Teng and S. M. Kang,
*Electrothermal Analysis of VLSI Systems,*Kluwer Academic Publishers, 2000. - C. H. Diaz, S. M. Kang, and C. Duvvury,
*Modeling of Electrical Overstress in Integrated Circuits,*Kluwer Academic Publishers, 1994.

- J. P. de Gyvez
- Survey papers (Yield and Reliability):
- Andrew Kahng's tutorial on Manufacturing Aware Design (ICCAD 2003).
- W. Kuo and T. Kim, "An Overview of Manufacturing Yield and
Reliability Modeling for Semiconductor Products,"
*Proceedings of the IEEE*, Vol. 87, August 1999. (Complete manuscript - figures have hyperlinks). - I. Koren and Z. Koren,
"Defect Tolerant VLSI Circuits: Techniques and Yield Analysis,"
*Proceedings of the IEEE*, Vol. 86, pp. 1817-1836, Sept. 1998. (Complete manuscript in PostScript format). - W. Maly, ``Computer-Aided Design for VLSI Circuit
Manufacturability,''
*Proceedings of IEEE,*vol. 78, no. 2, pp. 356-392, Feb. 1990. - I. Koren and A. D. Singh, ``Fault Tolerance in VLSI
Circuits,"
*Computer, Special Issue on Fault-Tolerant Systems,*vol. 23, pp. 73-83, July 1990. (Complete manuscript in PDF format). - I. Koren and C.H. Stapper, ``Yield Models for Defect
Tolerant VLSI Circuits: A Review,"
*Defect and Fault Tolerance in VLSI Systems*, vol. 1, I. Koren (ed.), pp. 1-21, Plenum, 1989. - W. Maly, W.R. Moore and A. Strojwas, ``Yield Loss
Mechanisms and Defect Tolerance,"
*Yield Modelling and Defect Tolerance in VLSI*, W.R. Moore, W. Maly and A. Strojwas (Eds.), pp. 3-30, Adam Hillger Ltd., 1988. - W. Maly, A.J. Strojwas and S.W. Director, ``VLSI Yield
Prediction and Estimation: A Unified Framework,"
*IEEE Trans. on Computer-Aided Design,*vol. CAD-5, no. 1, pp. 114-130, Jan. 1986. - C.H. Stapper, F.M. Armstrong and K. Saji, ``Integrated
Circuit Yield Statistics,"
*Proc. IEEE*, vol. 71, pp. 453-470, April 1983.

- Industrial perspectives (Yield):
- Cadence White papers on design for manufacturability.
- Intel Technology Journal,
- Y-E Hong
*et al.*"An Overview of Advanced Failure Analysis Techniques for Pentium and Pentium Pro Microprocessors," Intel Technology Journal, Q2, 1998. (Complete manuscript). - K. Seshan. T. Maloney and K. Wu, "The Quality and Reliability of Intel's Quarter Micron Process," Intel Technology Journal, Q3, 1998. (Complete manuscript).
- S. Mittal and P. McNally, "Line Defect Control to Maximize Yields," Intel Technology Journal, Q4, 1998. (Complete manuscript).
- N.H. Ramadan, "Redundancy Yield Model for SRAMS," Intel Technology Journal, Q4, 1997. (Complete manuscript).
- C.W. Hampson, "Redundancy and High-Volume Manufacturing Methods," Intel Technology Journal, Q4, 1997. (Complete manuscript - cache redundancy).
- R.S. Collica, J. Dietrich, R. Lambracht and D.G. Lau, ``A Yield
Enhancement Methodology for custom VLSI Manufacturing,''
*Digital Technical Journal*, vol. 4, no. 2, pp. 83-99, Spring 1992.

- Manufacturing Defects:
- C. H. Stapper, ``Modeling of Defects in Integrated
Circuit Photolithographic Patterns,''
*IBM J. Res. Develop*, vol. 28, no. 4, pp. 461-474, July 1984. - A.V. Ferris-Prabhu, ``Role of Defect Size Distribution
in Yield Modeling,''
*IEEE Trans. Electron Devices,*vol. ED-32, no. 9, pp. 1727-1736, Sept. 1985.

- C. H. Stapper, ``Modeling of Defects in Integrated
Circuit Photolithographic Patterns,''
- Critical area estimation:
- G.A. Allan and A.J. Walton, "Yield Prediction by Sampling with the
EYES tool,"
*Proc. of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems,*pp. 39-47, November 1996. (Complete manuscript in (compressed) PostScript format). - I. A. Wagner and I. Koren, "An Interactive VLSI CAD
Tool for Yield Estimation,"
*IEEE Trans. on Semiconductor Manufacturing,*Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 130-138, May 1995. (Abstract and a complete ps file). - P.K. Nag and W. Maly, ``Hierarchical Extraction of
Critical Area for Shorts and Very Large ICs,"
*Proceedings of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 19-27, Nov. 1995. - F. Duvivier and M. Rivier, ``Approximation of
Critical Areas of ICs with Simple Parameters Extracted From the
Layout,
*Proceedings of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 1-9, Nov. 1995. - G.A. Allan and J.A. Walton, ``Hierarchical Critical
Area Extraction with the EYE tool",
*Proceedings of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 28-36, Nov. 1995. - A. R. Dalal, P.D. Franzon and M.J. Lorenzetti, ``A Layout-Driven
Yield Predictor and Fault Generator for VLSI,''
*IEEE Trans. on Semiconductor Manufacturing*, vol. 6, no. 1, pp. 77-81, Feb. 1993. - J. P. Gyvez and C. Di, ``IC Defect Sensitivity
for Footprint-Type Spot Defects,''
*IEEE Trans. Computer-Aided Design,*vol. 11, no. 5, pp. 638-658, May 1992. - M. Lorenzetti, P. Magill, A. Dalal and P. Franzon,
``McYield: A CAD Tool for Functional Yield Projections,''
*IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 100-110, Nov. 1990. - S. Gandemer, B.C. Tremintin, J.J. Charlot, ``Critical Area and
Critical Levels Calculation in IC Yield Modeling",
*IEEE Trans. on Electron Devices*, vol. 35, pp.158-166, Feb. 1988.

- G.A. Allan and A.J. Walton, "Yield Prediction by Sampling with the
EYES tool,"
- Yield Models:
- C.N. Berglund, ``A Unified Yield Model Incorporating Both
Defect and Parametric Effects,"
*IEEE Trans. on Semiconductor Manufacturing,*vol. 9, pp. 447-454, August 1996. - C. Thibeault, Y. Savaria and J.L. Houle, ``Equivalence Proofs of
Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits,"
*IEEE Trans. on Computers*, Vol. 44, May 1995, pp. 723-726. - C.H. Stapper and R.J. Rosner, ``Integrated Circuit
Yield Management and Yield Analysis: Development and Implementation,"
*IEEE Trans. on Semiconductor Manufacturing,*vol. 8, pp. 95-102, May 1995. - I. Koren, Z. Koren and C.H. Stapper, ``A Statistical Study of
Defect Maps of Large Area VLSI ICs,"
*IEEE Trans. on VLSI Systems*, vol. 2, pp. 249-256, June 1994. - I. Koren, Z. Koren and C.H. Stapper, ``A Unified Negative
Binomial Distribution for Yield Analysis of Defect Tolerant Circuits,"
*IEEE Trans. on Computers*, vol. 42, pp. 724-437, June 1993. - J. A. Cunningham, ``The Use and Evaluation of Yield
Models in Integrated Circuit Manufacturing,''
*IEEE Trans. on Semiconductor Manufacturing*, vol. 3, no. 2, pp. 60-71, May 1990. - T.L. Michalka, R.C. Varshney, and J.D. Meindl, ``A
Discussion of Yield Modeling with Defect Clustering, Circuit
Repair, and Circuit Redundancy,"
*IEEE Trans. on Semiconductor Manufacturing,*vol. 3, pp. 116-127, Aug. 1990. - I. Koren, ``The Effect of Scaling on the Yield of VLSI Circuits,"
*Yield Modelling and Defect Tolerance in VLSI*, W. Moore, W. Maly and A. Strojwas (Eds.), pp. 91-99, Adam Hillger Ltd., Bristol, UK, 1988. (Complete manuscript in PDF format). - A.V. Ferris-Prabhu, L.D. Smith, H.A. Bonges and J.K. Paulsen,
``Radial Yield Variations in Semiconductor Wafers,"
*IEEE Circuits and Devices Magazine*, vol. 3, pp. 42-47, March 1987. - V. Foard Flack, ``Estimating Variations in IC Yield
Estimates,"
*IEEE J. of Solid-State Circuits*, vol. SC-21, pp. 362-365, April 1986. - V. Foard Flack, ``Introducing Dependency into IC Yield Models,"
*Solid-State Electronics*, vol. 28, no. 6, pp. 555-559, June 1985.

- C.N. Berglund, ``A Unified Yield Model Incorporating Both
Defect and Parametric Effects,"
- Defect Tolerant PLAs and Adders:
- Z. Chen and I. Koren. ``Techniques for Yield
Enhancement of VLSI Adders,"
*Proc. of ASAP 95 - the Internl. Conference on Application-Specific Array Processors,*pp. 222-229, July 1995. - N.J. Howard, A.M. Tyrell, and N.M. Allinson, ``The Yield
Enhancement of Field-Programmable Gate Arrays",
*IEEE Trans. VLSI Systems,*vol. 2, pp. 115-123, March 1994. - S.Y. Kuo and W. K. Fuchs, ``Fault Diagnosis and Spare
Allocation for Yield Enhancement in Large Reconfigurable PLA's,"
*IEEE Trans. on Computers,*vol. 41, pp. 221-226, Feb. 1992. - C.L. Wey, ``On Yield Considerations for the Design of
Redundant Programmable Logic Arrays,"
*IEEE Trans. on Computer-Aided Design*, vol. CAD-7, pp. 528-535, April 1988. - N. Wehn, M. Glesner, K. Caesar, P. Mann and A. Roth,
``A Defect Tolerant and Fully Testable PLA,"
*Proc. of the 25th Design Automation Conf.,*pp. 22-27, 1988.

- Z. Chen and I. Koren. ``Techniques for Yield
Enhancement of VLSI Adders,"
- Defect Tolerant Processors:
- R. Leveugle, Z. Koren, I. Koren, G. Saucier and N. Wehn, "The
HYETI Defect Tolerant Microprocessor: A Practical Experiment and a
Cost-Effectiveness Analysis,"
*IEEE Trans. on Computers*, Vol. 43, pp. 1398-1406, Dec. 1994. (Complete manuscript in PDF format). - M.W. Yung, M.J. Little, R.D. Etchells and J.G. Nash, ``Redundancy
for Yield Enhancement in the 3D Computer,"
*Proc. of Intern. Conf. on Wafer Scale Integration*, pp. 73-82, Jan. 1989. - M. Kuboschek, H.J. Iden, U. Jagau and J. Otterstedt,
``Implementation of a Defect Tolerant Large Area Monolithic
Multiprocessor System,"
*Int'l Conf. on Wafer Scale Integration,*pp. 28-34, 1992.

- R. Leveugle, Z. Koren, I. Koren, G. Saucier and N. Wehn, "The
HYETI Defect Tolerant Microprocessor: A Practical Experiment and a
Cost-Effectiveness Analysis,"
- Defect Tolerant Memories:
- C.H. Stapper, A.N. McLaren, and M. Dreckmann, ``Yield
Model for Productivity Optimization of VLSI Memory Chips with Redundancy
and Partially Good Product,"
*IBM J. Res. Develop.*, vol. 20, pp. 398-409, 1980. - I. Koren and Z. Koren, ``Yield Analysis of a Novel Scheme for
Defect-Tolerant Memories,"
*Proc. of the 1996 IEEE Intern. Conf. on Innovative Systems in Silicon,*pp. 269-278, Oct. 1996. - I. Koren and Z. Koren, ``Analysis of a Hybrid Defect-Tolerance
Scheme for High-Density Memory ICs,"
*Proc. of the 1997 IEEE Intern. Symp. on Defect and Fault Tolerance in VLSI Systems*, pp. 166-174, Oct. 1997. - T.P. Haraszti, ``A Novel Associative
Approach for Fault-Tolerant MOS RAM,"
*IEEE J. Solid-State Circuits,*pp. 539-546, June 1982. - H.L. Kalter, C.H. Stapper, J.E. Barth, J. Dilorenzo,
C.E. Drake, J.A. Fifield, G.A. Kelley, S.C. Lewis, W.B. Van Der
Hoeven and J.A. Yankosky,
"A 50-ns 16Mb DRAM with 10-ns Data Rate and On-Chip ECC,"
*IEEE J. of Solid-State Circuits,*pp. 1118-1128, Oct. 1990. - T. Kirihata, Y. Watanabe, H. Wong and J.K. DeBrosse,
``Fault-Tolerant Designs for 256 Mb DRAM,"
*IEEE J. of Solid-State Circuits*, vol. 31, pp. 558-566, April 1996. - G. Kitsukawa, M. Horiguchi, Y. Kawajiri and T. Kawahara,
``256-Mb DRAM Circuit Technologies for File Applications,"
*IEEE J. of Solid-State Circuits*, vol. 28, pp. 1105-11101 Nov. 1993. - C.H. Stapper, ``Block Alignment: A Method for
Increasing the Yield of Memory Chips that are Partially Good,"
*Defect and Fault Tolerance in VLSI Systems,*I. Koren (ed.), pp. 243-255, New York: Plenum, 1989. - T. Sugibayashi, I. Naritake, S. Utsugi, K. Shibahara and R.
Oikawa, ``A 1-Gb DRAM for File Applications,"
*IEEE J. of Solid-State Circuits*, vol. 30, pp. 1277-1280, Nov. 1995. - T. Yamagata, H. Sato, K. Fujita, Y. Nishmura and K. Anami, ``A
Distributed Globally Replaceable Redundancy Scheme for Sub-Half-micron
ULSI Memories and Beyond,"
*IEEE J. of Solid-State Circuits*, vol. 31, pp. 195-201, Feb. 1996. - J-H. Yoo, C-H. Kim, K-C. Lee and K-H. Kyung, ``A 32-Bank 1Gb
Self-Strobing Synchronous DRAM with 1GB/s Bandwidth,"
*IEEE J. of Solid-State Circuits*, vol. 31, pp. 1635-1643, Nov. 1996.

- C.H. Stapper, A.N. McLaren, and M. Dreckmann, ``Yield
Model for Productivity Optimization of VLSI Memory Chips with Redundancy
and Partially Good Product,"
- Layout Modifications for Yield Enhancement:
- G.A. Allan, A.J. Walton and R.J. Holwill, ``A Yield
Improvement Technique for IC Layout Using Local Design Rules,''
*IEEE Trans. on Computer-Aided Design,*vol. 11, no. 11, pp. 1355-1362, Nov. 1992. - C. Bamji and E. Malavasi, ``Enhanced Network Flow
Algorithm for Yield Optimization,"
*Proc. of the 33rd Design Automation Conference, DAC-96,*pp. 746-751, June, 1996. - Z. Chen and I. Koren. ``Layer Assignment for Yield
Enhancement,"
*Proc. of the 1995 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 173-180, Nov. 1995. - V.K.R. Chiluvuri and I. Koren, "Layout Synthesis
Techniques for Yield Enhancement,"
*IEEE Trans. on Semiconductor Manufacturing,*Vol. 8, Special Issue on Defect, Fault, and Yield Modeling, pp. 178-187, May 1995. (Complete text in (compressed) PostScript format). - V.K.R. Chiluvuri and I. Koren, ``New Routing and
Compaction Strategies for Yield Enhancement,''
*IEEE Int. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 325-334, Nov. 1992. - V.K.R. Chiluvuri and I. Koren, ``Topological Optimization of PLAs
for Yield Enhancement,"
*Proc. of the 1993 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 175-182, Oct. 1993. - V.K.R. Chiluvuri, I. Koren and J. L. Burns, ``The
Effect of Wire Length Minimization on Yield,"
*Proc. of the 1994 IEEE Internl. Workshop on Defect and Fault Tolerance in VLSI Systems*, pp. 97-105, Oct. 1994 - V.K.R. Chiluvuri and I. Koren, ``Wire Length and Via
Reduction for Yield Enhancement,"
*Proc. of the 1996 SPIE Microelectronics Manufacturing Conference,*pp. 103-111, Oct. 1996. - N. Maldonado, G. Andrus, A. Tyagi, M. Madani and M.
Bayoumi, ``A Post-Processing Algorithm
for Short-Circuit Defect Sensitivity reduction in VLSI Layouts,''
*IEEE Int. Conference on Wafer Scale Integration,*San Francisco, CA, pp. 288-297, 1995.

- G.A. Allan, A.J. Walton and R.J. Holwill, ``A Yield
Improvement Technique for IC Layout Using Local Design Rules,''
- Routing Modifications for Yield Enhancement:
- E.P. Huijbregts, H. Xue and J.A.G. Jess, ``Routing
for Reliable Manufacturing,"
*IEEE Trans. on Semiconductor Manufacturing,*vol. 8, pp. 188-194, May 1995. - S. Y. Kuo, ``YOR: A Yield-Optimizing Routing Algorithm by
Minimizing Critical Areas and vias,''
*IEEE Trans. Computer-Aided Design*, vol. 12, no. 9, pp. 1303-1311, Sept. 1993. - A. Pitaksanonkul, S. Thanawastien, C. Lursinsap and J.A.
Gandhi, ``DTR: A Defect-Tolerant Routing Algorithm,''
*26st IEEE Design Automation Conference,*pp. 795-798, 1989. - A. Venkataraman, H. Chen and I. Koren, ``Yield Enhanced
Routing for High-Performance VLSI Designs,"
*Proc. of the Microelectronics Manufacturing Yield, Reliability and Failure Analysis, SPIE'97,*pp. 50-60, Oct. 1997.

- E.P. Huijbregts, H. Xue and J.A.G. Jess, ``Routing
for Reliable Manufacturing,"
- Floorplanning and Yield:
- Z. Koren and I. Koren, "On the Effect of
Floorplanning on the Yield of Large Area Integrated Circuits,"
*IEEE Trans. on VLSI Systems*, Vol. 5, pp. 3-14, March 1997. (Complete manuscript in PostScript format). - I. Koren and Z. Koren,
"Incorporating Yield Enhancement into the Floorplanning Process,"
*IEEE Trans. on Computers, Special Issue on Defect Tolerance in Digital Systems,*, Vol. 49, pp. , June 2000. (Complete manuscript in PostScript format).

- Z. Koren and I. Koren, "On the Effect of
Floorplanning on the Yield of Large Area Integrated Circuits,"
- Reliability Estimation and Enhancement:
- R. Burch, F. Najm, P. Yang and D. Hocevar, "Pattern-Independent
Current Estimation for Reliability Analysis of CMOS Circuits,"
*25th ACM/IEEE Design Automation Conference,*pp. 294-299, June 1988. - Z. Chen and I. Koren,
"Three Layer Routing for Reliability Enhancement,"
*Journal of Microelectronic Systems Integration*, Vol 5, No 4, pp. 209-219, Dec. 1997. (Complete manuscript in (compressed) PostScript format). - Y.H. Shih, Y. Leblebici and S. M. Kang, "ILLIIADS: A Fast Timing and
Reliability Simulator for Digital MOS Circuits,"
*IEEE Trans. on Computer-Aided Design,*Vol. 12, pp. 1387-1402, September 1993.

- R. Burch, F. Najm, P. Yang and D. Hocevar, "Pattern-Independent
Current Estimation for Reliability Analysis of CMOS Circuits,"
- Hot Carrier Reliability:
- D.B. Jackson, D. Bell, B. Doyle, B. Fishbein and D. Krakauer,
``Transistor Hot Carrier Reliability Assurance in CMOS
Technologies,''
*Digital Technical Journal*, vol. 4, no. 2, pp. 100-113, Spring 1992. - Y. Leblebici and S. M. Kang,
*Hot-Carrier Reliability of MOS VLSI Circuits,*Kluwer Academic Publishers, 1993. - Y. Leblebici and S. M. Kang, "Simulation of Hot-Carrier Induced MOS
Circuit Degradation for VLSI Reliability Analysis,"
*IEEE Trans. on Reliability,*Vol. 43, pp. 197-206, June 1994. - Y. Leblebici, "Design Considerations for CMOS Digital Circuits with
Improved Hot-Carrier Reliability,"
*IEEE Journal of Solid-State Circuits,*Vol. 31, pp. 1014-1024, July 1996. (Complete manuscript in PostScript format). - P.-C. Li and I.N. Hajj, ``Computer-Aided Redesign of VLSI Circuits
for Hot-Carrier Reliability,"
*IEEE Trans. on Computer-Aided Design,*Vol. 15, pp. 453-464, May 1996.

- D.B. Jackson, D. Bell, B. Doyle, B. Fishbein and D. Krakauer,
``Transistor Hot Carrier Reliability Assurance in CMOS
Technologies,''
- Electromigration Reliability:
- J. Clement, E. Atakov and J. Lloyd,
``Electromigration Reliability of VLSI Interconnect,''
*Digital Technical Journal*, vol. 4, no. 2, pp. 114-125, Spring 1992. - G. Yoh and F. Najm, "A Statistical Model for Electromigration
Failures,"
*IEEE Sympos. on Quality Electronic Design,*pp. 45-50, March 2000. (This and other papers can be found here). - C. Teng, Y-K. Cheng, E. Rosenbaum and S. M. Kang, "Hierarchical
Electromigration Reliability Diagnosis for VLSI Interconnects,"
Current Estimation for Reliability Analysis of CMOS Circuits,"
*1996 ACM/IEEE Design Automation Conference,*pp. 752-757, June 1996. (Complete manuscript in PostScript format). (Complete manuscript in PDF format). (Other related papers in DAC'96). (Other related papers in DAC). - Picture 1 of electromigration damage.
- Picture 2 of electromigration damage.

- J. Clement, E. Atakov and J. Lloyd,
``Electromigration Reliability of VLSI Interconnect,''
- Optical Simulation:
- K. Adam, Y. Granik, A. Torres, and N. B. Cobb, "Improved
modeling performance with an adapted vectorial formulation of the
Hopkins imaging equation," in
*Optical Microlithography XVI. Edited by Yen, Anthony. Proceedings of the SPIE, Vol. 5040, pp. 78-91 (2003).*, pp. 78-91, June 2003. - J. D. Byers, M. D. Smith, and C. A. Mack, "3D lumped parameter
model for lithographic simulations," in
*Proc. SPIE Vol. 4691, p. 125-137, Optical Microlithography XV, Anthony Yen; Ed.*, pp. 125-137, July 2002. - H. H. Hopkins, "On the diffraction theory of optical images,"
*Proc. Royal Soc. Series*, vol. 217, no. 1131, pp. 408-432, 1953. - Y. Pati, A. Ghazanfarian, and R. Pease, "Exploiting structure in
fast aerial image computation for integrated circuit patterns,"
*IEEE Transactions Semiconductor Manufacturing*, vol. 10, pp. 62-74, Feb. 1997.

- K. Adam, Y. Granik, A. Torres, and N. B. Cobb, "Improved
modeling performance with an adapted vectorial formulation of the
Hopkins imaging equation," in
- Photo-resist modeling:
- M. D. Smith, J. D. Byers, and C. A. Mack, "Comparison
between the process windows calculated with full and simplied resist
models," in
*Proc. SPIE Vol. 4691, p. 1199-1210, Optical Microlithography XV, Anthony Yen; Ed.*, pp. 1199-1210, July 2002.

- M. D. Smith, J. D. Byers, and C. A. Mack, "Comparison
between the process windows calculated with full and simplied resist
models," in
- CMP modeling:
- G. Nanz and L. E. Camilletti, "Modeling of chemical-mechanical
polishing: A review,"
*IEEE Trans. on Semiconductor Manufacturing*, vol. 8, no. 4, pp. 382-389, 1995.

- G. Nanz and L. E. Camilletti, "Modeling of chemical-mechanical
polishing: A review,"
- OPC/CMP Layout improvement techniques:
- L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang,
"Toward a methodology for manufacturability driven design rule
exploration,” in
*Proc. Design Automation Conf.*, (New York, NY, USA), pp. 311-316, ACM Press, 2004. - Y. Chen, A. B. Kahng, G. Robins, and A. Zelikovsky, "Practical
iterated fill synthesis for cmp uniformity," in
*Proc. Design Automation Conf.*, pp. 671-674, ACM Press, 2000. - N. B. Cobb,
*Fast Optical and Process Proximity Correction Algorithms for Integrated Circuit Manufacturing*. PhD thesis, University of California at Berkeley, 1998. - L.-D. Huang and M. D. F. Wong, "Optical proximity correction
(OPC)-friendly maze routing," in
*Proc. Design Automation Conf.*, 2004. - P. Gupta, A. B. Kahng, and C.-H. Park, "Detailed placement for
improved depth of focus and CD control," in
*Proc. Asia and South Pacific Design Automation Conf.*, 2005. - P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang, "A cost-driven
lithographic correction methodology based on off-the-shelf sizing
tools," in
*Proc. Design Automation Conf.*, (New York, NY, USA), pp. 16-21, ACM Press, 2003. - A. B. Kahng, "Research direcitons for coevolution of rules and
routers," in
*Proc. Int. Symp. on Physical Design*, pp. 122-125, ACM Press, 2003. - H. K.-S. Leung, "Advanced routing in changing technology
landscape," in
*Proc. Int. Symp. on Physical Design*, pp. 118-121, ACM Press, 2003. - L. W. Liebman, "Layout impact of resolution enhancement techniques:
impediment or opportunity?," in
*Proc. Int. Symp. on Physical Design*, pp. 110-117, 2003. - G.Y. Liu, R.F. Zhang, K. Hsu and L. Camilletti, "Chip-level CMP
Modeling and Smart Dummy for HDP and Conformal CVD Films,"
*Proc. of CMPMIC 99,*pp.120-127, 1999. Available at http://arxiv.org/abs/cs.CE/0011014 - J. Mitra, P. Yu, and D. Z. Pan, "RADAR: RET-aware detailed routing
using fast lithography simulations," in
*Proc. Design Automation Conf.*, 2005. - H. Ren, D. Z. Pan, C. A. Alpert, and P. Villarrubia, "Diffusion
based placement migration," in
*Proc. Design Automation Conf.*, 2005. - R. Tian, D.F. Wong and R. Boone, "Model-based dummy feature
placement for oxide CMP manufacturability,"
*IEEE Transactions on computer aided design of integrated circuits and systems,*July 2001. - X. Yuan, K. W. McCullen, F.-L. Heng, R. F. Walker, J. Hibbeler, R.
J. Allen, and R. R. Narayan, "Technology migration technique for
designs with strong ret-driven layout restrictions,"
in
*ISPD '05: Proceedings of the 2005 international symposium on physical design*, (New York, NY, USA), pp. 175-182, ACM Press, 2005. - S. Zhang and W. Dai, "TEG: A new post-layout optimization method,"
*IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems*, vol. 22, pp. 446-456, Apr. 2003.

- L. Capodieci, P. Gupta, A. B. Kahng, D. Sylvester, and J. Yang,
"Toward a methodology for manufacturability driven design rule
exploration,” in
- Timing Application after OPC:
- J. Yang, L. Capodieci, and D. Sylvester, "Advanced timing analysis
based on post-opc extraction of critical dimensions," in
*DAC 05: Proceedings of the 42nd annual conference on Design automation*, (New York, NY, USA), pp. 359-364, ACM Press, 2005.

- J. Yang, L. Capodieci, and D. Sylvester, "Advanced timing analysis
based on post-opc extraction of critical dimensions," in

Created by Prof. Israel Koren, koren at ecs.umass.edu