UNIVERSITY OF MASSACHUSETTS
Department of Electrical and Computer Engineering

Fault Tolerant Computing - ECE655

References:

• Fundamental concepts
  • A conceptual framework for system fault tolerance (from the High Integrity Software Systems Assurance program of NIST - National Institute of Standards and Technbology)
  • A. Avizienis and J. Laprie, ``Dependable Computing: From Concepts to Design Diversity,'' Proc. IEEE, vol.74, no.5, pp.629-638, May 1986.
  • A.K. Somani and N.H. Vaidya, ``Understanding fault-tolerance and reliability,'' IEEE Computer, vol.30, no.4, pp.45-50, Apr. 1997.
  • Reliability - Definitions and Terminology (pdf file, written by Frank Doerenberg)
• Books:
  • D.K. Pradhan (ed.), Fault Tolerant Computer System Design, Prentice-Hall, 1996.
  • D.P. Siewiorek and R.S. Swarz, Reliable Computer Systems: Design and Evaluation, A.K. Peters, 1998.
  • B.W. Johnson, Design and Analysis of Fault-Tolerant Digital Systems, Addison-Wesley, 1989.
  • P. Jalote, Fault Tolerance in Distributed Systems, PTR Printice Hall, 1994.
• Software Fault Tolerance:
  • N. Leveson, J. Knight, and T. Shimeall, ``The use of self check and voting in software error detection: An empirical study,'' IEEE transactions on Software Engineering, April 1990.
  • A. Avizienis and J. Kelly, ``Fault Tolerance by Design Diversity: Concepts and Experiments,'' IEEE Computer, August 1984, pp. 67-80.
  • J.H. Purtilo and P. Jalote, ``An environment for developing fault-tolerant software,'' IEEE Trans. Software Engg., vol.17, no.2, pp.153-159, Feb. 1991.
• General Fault Tolerance:
  • A. Agbaria and J.S. Plank. Design, implementation, and performance of checkpointing in NetSolve. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 49-54, June 2000.
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  • Z. Al-Ars and A. van de Goor. Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs. In Proceedings of the Design Automation and Test in Europe (DATE), pages 496-503, March 2001.
  • H. Al-Asaad, J.P. Hayes, and T. Mudge. Modeling and Detecting Control Errors in Microprocessors. In Proceedings ofDYCONS, August 1999.
  • Z. Alkhalifa, V.S.S. Nair, N. Krishnamurthy, and J.A. Abraham. Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection. IEEE Transactions on Parallel and Distributed Systems, 10(6):627-641, June 1999.
  • L. Anghel and M. Nicolaidis. Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. In Proceedings of the Design Automation and Test in Europe (DATE), pages 591-598, March 2000.
  • T. Austin. DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 196-207, November 1999.
  • A. Benso, S. Chiusano, P. Prinetto, and L. Tagliaferri. A C/C++ source-to-source compiler for dependable applications. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 71-78, June 2000.
  • A. Benso, S.Chiusano, G.Di Natale, and P.Prinetto. An on-line BIST RAM architecture with self-repair capabilities. IEEE Transactions on Reliability, 51(1):123-128, March 2002.
  • P. Bose. Ensuring dependable processor performance: an experience report on pre-silicon performance validation. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 481-486,July 2000.
  • D.C. Bossen, A. Kitamom, K.F. Reick, and M.S. Floyd. Fault-Tolerant Design of the IBM pSeries 690 System Using POWER4 Processor Technology. IBM Journal of Research and Development, 46(1):77-86, January 2002.
  • D.C. Bossen, J.M. Tendler, and K. Reick. POWER4 System Design for High Reliability. IEEE Micro, 22(2): 16-24, March 2002.
  • S. Chatterjee, C. Weaver, and T. Austin. Efficient Checker Processor Design. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 87-97, December 2000.
  • C. Chen and A. K. Somani. Fault Containment in Cache Memories for TMR Redundant Processor Systems. IEEE Transactions on Computers, 48(4):386-397, March 1999.
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  • T.J. Dell. A White Paper on the Benefits of Chipkill-Correct ECC for PC Serve Main Memory, IBM Microelectronics Division, November 1997.
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  • Itanium Processor Family Error Handling Guide, August 2001. http://www.intel.com/design/itanium/downloads/249278.htm.
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  • C. K. Kouba and G. Choi, "The single event upset characteristics of the 486-DX4 microprocessor," IEEE Radiation Effects Data Workshop, pp. 48-52, 1997.
  • S. Kim and A.K. Somani. An Adaptive Write Error Detection Technique in On-Chip Caches of Multi-Level Caching Systems. Journal of Microprocessors and Microsystems, 22(9):561-570, March 1999.
  • S. Kim and A.K. Somani. Area Efficient Architectures for Information Integrity in Cache Memories. In Proceedings of the International Symposium of Computer Architecture (ISCA), pages 246-255, May 1999.
  • S. Kim and A.K. Somani. On-Line Integrity Monitoring of Microprocessor Control Logic. Microelectronics Journal, 32(12):999-1007, December 2001.
  • S. Kim and A. K. Somani, "SSD: an affordable fault tolerance for superscalar processors," Int'l Proc. Pacific Rim Symp. Dependable Computing, 2001.
  • S. Kim and A. K. Somani, "Adaptive write error detection technique in on-chip caches of multi-level caching systems," Microprocessors and Microsystems Journal, 22(9):561-570, March 1999.
  • S. Kim and A. K. Somani, "On-line integrity monitoring of microprocessor control logic," Proc. Int'l Conf. Computer Design, pp. 314-319, 2001.
  • S. Kim and A. K. Somani, "An affordable transient fault tolerance for superscalar processors," Fast Abstract in conjunction with IEEE DSN-2001, pp. 10-11, Goteborg, June 2001.
  • S. Kim and A. K. Somani, "On-line integrity monitoring of microprocessor control logic," Microelectronics Journal, 32(12):999-1007, Nov. 2001.
  • S.W. Kwak, B.J. Choi, and B.K. Kim. An optimal checkpointing-strategy for real-time control systems under transient faults. IEEE Transactions on Reliability, 50(3):293-301, September 2001.
  • J.L. Lawall and G. Muller. Efficient incremental checkpointing of Java programs. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 61-70, June 2000.
  • P. Liggesmeyer and 0. Maeckel. Quantifying the reliability of embedded systems by automated analysis. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 89-94, July 2000.
  • J. Li and E. E. Swartzlander, "Concurrent error detection in ALUs by recomputing with rotated operands," Proc. Int'l Workshop Defect and Fault Tolerance in VLSI Systems, pp. 109-116, 1992.
  • C-Y. Lin, S-Y. Kuo, and Y. Huang. A checkpointing tool for Palm operating system. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 71-76, July 2000.
  • A. Maamar, G. Russell, "A 32 bit RISC processor with concurrent error detection," Proc. Euromicro Conf., pp. 461-467, 1998.
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  • I. Majzik, W. Hohl, A. Pataricza, and V. Sieh, "Multiprocessor checking using watchdog processors," Computer Systems Science and Engineering, 11(5):301-310, Sept. 1996.
  • A. Mendelson and N. Suri, "Designing high-performance and reliable superscalar architectures-the out of order reliable superscalar (03RS) approach," Proc. Int'l Conf. Dependable Systems and Networks, pp. 473-481, 2000.
  • A. Messer, P. Bemadat, F. Fu, D. Chen, Z. Dimitrijevic, D. Lie, D.D. Mannaru, A. Riska, and D.Milojicic. Susceptibility of Modem Systems and Software to Soft Errors. Technical Report HPL-2001-43, HP Laboratories, March 2001.
  • D. Milojicic, A. Messer, J. Shau, G. Fu, and A. Munoz. Increasing Relevance of Memory Hardware Errors - A Case for Recoverable Programming Models. In Proceedings of the ACM SIGOPS European Workshop, September 2000.
  • G. Miremadi and J. Torin, "Effects of physical injection of transient faults on control flow and evaluation of some software-implemented error detection techniques," Proc. Dependable Computing for Critical Applications 4, PP- 435-457, 1995.
  • G. Miremadi and J. Torin, "Evaluating processor- behavior and three error-detection mechanisms using physical fault-injection," IEEE Trans. Reliability, 44(3):441-454, Sept. 1995.
  • W. A. Moreno et al., "First test results of system level fault tolerant design validation through laser fault injection," Proc. Int'l Conf. Computer Design: VLSI in Computers and Processors, pp. 544-548, 1997.
  • S. S. Mukherjee, M. Kontz, and S. K. Reinhardt, "Detailed design and evaluation of redundant multi-threading alternatives", Proceedings of the 29th Annual International Symposium on Computer Architecture, pp. 99-110, 2002.
  • NonStop Computing, http://nonstop.compaq.com/. N. Oh. Software Implemented Hardware Fault Tolerance. PhD thesis, Stanford University, 2000.
  • J. B. Nickel and A. K. Somani, "REESE: A method of soft error detection in microprocessors," Proc. Int'l Conf. Dependable Systems and networks, pp. 401-410, 2001.
  • M. Nicolaidis, "Design for soft-error robustness to rescue deep submicron scaling," Proc. Int'l Test Conf., pp. 1140, 1998.
  • N. Oh, P.P. Shirvani, and E.J. McCluskey. Control Flow Checking by Software Signatures. IEEE Transactions on Reliability, 51(1):111-122, March 2002.
  • N. Oh, P.P. Shirvani, and E.J. McCluskey. Error Detection by Duplicating Instructions in Super-scalar Processors. IEEE Transactions on Reliability, 51(1):63-75, March 2002.
  • J. Ohisson and M. Rimen, "Implicit signature checking," Int'l Symp. Fault-Tolerant Computing, pp. 218-227, 1995.
  • J. Opiinger and M. Lam. Enhancing Software Reliability using Speculative Threads. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), October 2002.
  • S. J. Patel, Z. Kalbarczyk, R. K. lyer, W. Magda, and N. Nakka. A Processor-Level Framework for High-Performance and High-Dependability. In Proceedings of the Workshop on Evaluating and Architecting Systems for Dependability, 2001.
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  • F. Rashid, K.K. Saluja, and P. Ramanathan. Fault tolerance through re-execution in multiscalar architecture. In Proceedings of the International Conference on Dependable Systems and Networks (DSN), pages 482-491, June 2000.
  • J. Ray, J. Hoe, and B. Falsafi. Dual Use of Superscalar Datapath for Transient-Fault Detection and Recovery. In Proceedings of the International Symposium on Microarchitecture (MICRO), pages 214-224, December 2001.
  • S. K. Reinhardt and S. S. Mukherjee, "Transient fault detection via simultaneous multithreading," Proc, Int'l Symp. Computer Architecture, pp. 25-36, 2000.
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  • E. Rotenberg, "AR-SMT: A microarchitectural approach to fault tolerance in microprocessor," Proc. Int'l Symp. Fault-Tolerant Computing, 1999.
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