Sample Final - Selected solutions

Problem 1:
(a) PCV=1001 (c) 0.5.
----------------------------------------------
Problem 2:
(b) 157 cycles (c) 279 cycles.
----------------------------------------------
Problem 3:
For all 3 models the silicon area required for the instruction
cache is:
(1) Data RAM - 4K * 8 * 0.001 = 32.8
(2) Tag RAM - [(32- log_2 16 - log_2 (4K/16)+1] * (4K/16) * 0.001 = 5.4

For models A & T the silicon area required for the data cache is:
(1) Data RAM  = 32.8
(2) Tag RAM - [(32- log_2 64 - log_2 (4K/64)+1] * (4K/64) * 0.001 = 1.3

For model V the silicon area required for the vector registers is:
    8 * 64 * 64 * 0.0002 = 65.5

For model T the silicon area required for the reservation stations is:
 At least four reservation stations = 0.4

For model T the silicon area required for the Load and Store buffers 
is (see textbook):
   Load buffer - 6 * 64 * 0.002 = 0.8
   Store buffer - 3 * (32 + 64) * 0.002 = 0.6

The total area requirements are approximately:
 Model A         Model T           Model V
   81.3            85.1              113.7 
----------------------------------------------
Problem 4:
(a) CPU_limit= 80 TPS (transaction per second), 
disk_space= 800MB requiring either 3 300MB disks or 6 150MB disks.
To get a rate of 80 TPS we need either 6 300MB disks or 4 150MB disks. 
To satisfy size and rate requirments we need 6 disks of either type.
(b) For type 1: 81.8%, for type 2: 89.1%.
----------------------------------------------
Problem 5:
(a) 40=32+8 and 72=32+16+16+8
(b) 1. Small effect, 2. No effect, 3. Large effect, 4. Small effect.
----------------------------------------------