sim-cache: SimpleScalar/PISA Tool Set version 3.0 of August, 2003. Copyright (c) 1994-2003 by Todd M. Austin, Ph.D. and SimpleScalar, LLC. All Rights Reserved. This version of SimpleScalar is licensed for academic non-commercial use. No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com). sim: command line: ../simplesim-3.0/sim-cache -config lab3_cache1.cfg -redir:sim sim_lab3_cache1 test-math sim: simulation started @ Mon Mar 19 15:29:27 2007, options follow: sim-cache: This simulator implements a functional cache simulator. Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs. No timing information is generated. # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed 1 # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt # restore EIO trace execution from # -redir:sim sim_lab3_cache1 # redirect simulator output to file (non-interactive only) # -redir:prog # redirect simulated program output to file -nice 0 # simulator scheduling priority -max:inst 0 # maximum number of inst's to execute -cache:dl1 dl1:64:64:1:l # l1 data cache config, i.e., {|none} -cache:dl2 dl2:128:64:1:l # l2 data cache config, i.e., {|none} -cache:dl3 dl3:256:64:1:l # l3 data cache config, i.e., {|none} -cache:il1 il1:64:64:1:l # l1 inst cache config, i.e., {|dl1|dl2|none} -cache:il2 il2:128:64:1:l; # l2 instruction cache config, i.e., {|dl2|none} -cache:il3 il3:256:64:1:l; # l3 instruction cache config, i.e., {|dl2|none} -tlb:itlb none # instruction TLB config, i.e., {|none} -tlb:dtlb none # data TLB config, i.e., {|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32-bit inst equivalents # -pcstat # profile stat(s) against text addr's (mult uses ok) The cache config parameter has the following format: :::: - name of the cache being defined - number of sets in the cache - block size of the cache - associativity of the cache - block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-random Examples: -cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments. Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l sim: ** starting functional simulation w/ caches ** sim: ** simulation statistics ** sim_num_insn 213553 # total number of instructions executed sim_num_refs 56885 # total number of loads and stores executed sim_elapsed_time 1 # total simulation time in seconds sim_inst_rate 213553.0000 # simulation speed (in insts/sec) il1.accesses 213553 # total number of accesses il1.hits 193067 # total number of hits il1.misses 20486 # total number of misses il1.replacements 20422 # total number of replacements il1.writebacks 0 # total number of writebacks il1.invalidations 0 # total number of invalidations il1.miss_rate 0.0959 # miss rate (i.e., misses/ref) il1.repl_rate 0.0956 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il2.accesses 20486 # total number of accesses il2.hits 5045 # total number of hits il2.misses 15441 # total number of misses il2.replacements 15313 # total number of replacements il2.writebacks 0 # total number of writebacks il2.invalidations 0 # total number of invalidations il2.miss_rate 0.7537 # miss rate (i.e., misses/ref) il2.repl_rate 0.7475 # replacement rate (i.e., repls/ref) il2.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) il3.accesses 25972 # total number of accesses il3.hits 15441 # total number of hits il3.misses 10531 # total number of misses il3.replacements 10275 # total number of replacements il3.writebacks 0 # total number of writebacks il3.invalidations 0 # total number of invalidations il3.miss_rate 0.4055 # miss rate (i.e., misses/ref) il3.repl_rate 0.3956 # replacement rate (i.e., repls/ref) il3.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il3.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 57466 # total number of accesses dl1.hits 56348 # total number of hits dl1.misses 1118 # total number of misses dl1.replacements 1054 # total number of replacements dl1.writebacks 625 # total number of writebacks dl1.invalidations 0 # total number of invalidations dl1.miss_rate 0.0195 # miss rate (i.e., misses/ref) dl1.repl_rate 0.0183 # replacement rate (i.e., repls/ref) dl1.wb_rate 0.0109 # writeback rate (i.e., wrbks/ref) dl1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl2.accesses 1743 # total number of accesses dl2.hits 1120 # total number of hits dl2.misses 623 # total number of misses dl2.replacements 495 # total number of replacements dl2.writebacks 326 # total number of writebacks dl2.invalidations 0 # total number of invalidations dl2.miss_rate 0.3574 # miss rate (i.e., misses/ref) dl2.repl_rate 0.2840 # replacement rate (i.e., repls/ref) dl2.wb_rate 0.1870 # writeback rate (i.e., wrbks/ref) dl2.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl3.accesses 949 # total number of accesses dl3.hits 637 # total number of hits dl3.misses 312 # total number of misses dl3.replacements 96 # total number of replacements dl3.writebacks 86 # total number of writebacks dl3.invalidations 0 # total number of invalidations dl3.miss_rate 0.3288 # miss rate (i.e., misses/ref) dl3.repl_rate 0.1012 # replacement rate (i.e., repls/ref) dl3.wb_rate 0.0906 # writeback rate (i.e., wrbks/ref) dl3.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) ld_text_base 0x00400000 # program text (code) segment base ld_text_size 91744 # program text (code) size in bytes ld_data_base 0x10000000 # program initialized data segment base ld_data_size 13028 # program init'ed `.data' and uninit'ed `.bss' size in bytes ld_stack_base 0x7fffc000 # program stack segment base (highest address in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0x00400140 # program entry point (initial PC) ld_environ_base 0x7fff8000 # program environment base address address ld_target_big_endian 0 # target executable endian-ness, non-zero if big endian mem.page_count 33 # total number of pages allocated mem.page_mem 132k # total size of memory pages allocated mem.ptab_misses 34 # total first level page table misses mem.ptab_accesses 1545387 # total page table accesses mem.ptab_miss_rate 0.0000 # first level page table miss rate