Comparison of Dynamic Voltage Scaling Algorithms
Dynamic Voltage Scaling has been a key technique for exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and the operating frequency. The DVS algorithms are shown to make dramatic energy savings while providing the necessary peak computation power in general purpose systems. However, to provide real time guarantees, DVS must consider the deadlines and periodicity of real time tasks. In this project, I have attempted to simulate three of the five algorithms published in the paper by Pillai and Shin, "Real Time Dynamic Voltage Scaling for Low Power Embedded Operating Systems"
Dynamic Voltage Scaling tries to address the tradeoff between performance and battery life by taking into account two important characteristics:
1. the peak computing rate needed is much higher than the average throughput that must be sustained.
This essentially means that high performance is needed only for a small fraction of the time, while fr the rest of the time, a low performance low power processor would suffice. We can achieve the low performance by lowering the operating frequency of the processor when the full speed is not needed. DVS scales the operating voltage along with the frequency which results in power savings.
2. the processors are based on CMOS Logic
CMOS Logic has a voltage dependent maximum operating frequency, so when used at a reduced frequency, the processor can operate at a lower supply voltage. Since the energy dissipated per cycle with the CMOS scales quadratically to the supply voltage, DVS can potentially provide a very large net energy savings through frequency and voltage scaling
In this project, I have tried to simulate three of the five algorithms proposed by Pillai and Shin in their paper, "Real Time Dynamic Voltage Scaling for Embedded Operating Systems". Besides, the standard non-DVS "Rate Monotonic" and "Earliest Deadline First" algorithms have also been simulated. Finally, the gantt chart of these algorithms for the various tasks are output and the corresponding energy savings achieved from the DVS algorithms as compared to the non-DVS algorithms is displayed.
The Non-DVS algorithms simulated are:
1. Rate Monotonic Algorithm
2. Earliest Deadline First Algorithm
The DVS algorithms simulated are :
1. Static Rate Monotonic Algorithm
2. Static Earliest Deadline First Algorithm
3. Cycle Conserving Earliest Deadline First Algorithm
In Static Voltage Scaling, we select the lowest possible operating frequency that will allow the RM or EDF scheduler to meet all the deadlines for a give task set. This frequency is set statically and will not be changed unless the task set is changed.
Generally, real time tasks use much less than their specified worst case computation requirements on most invocations. To account for this, the cycle conserving mechanism reduces the operating frequency and voltage when tasks use less than their worst case allotment and increase the frequency to meet the worst case needs.
1.All tasks are periodic i.e. the task Ti is released periodically once every Pi time units
2.The task needs to complete its execution by its deadline, i.e. Deadline equals Period
3.Tasks are independent and non-preemptive
HELP (with example testcases)