Number of ROB entries: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Number of CDBs: 1 2
Number of Load Buffers:
Latency of Load: clock cycle(s)
# of Instructions to 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
current # of Instructions: