Introduction
to M-Sim
M-Sim is an open source computer architecture simulator developed
by Joseph Sharkey while he was a PhD student at the State University of New
York at
As a computer architecture simulator, M-Sim
provides designers and researchers a platform by which they can measure the
performance of new devices. Categorized as a flexible, multi-threaded,
microarchitectural simulation environment, it provides detailed performance
analysis for superscalar microprocessors. It is a C language program intended
for UNIX platforms.
M-Sim is an extension of the well-known
simulator SimpleScalar (see [2] for further information on SimpleScalar). M-Sim
extends simplescalar in four key areas.
Through a series of lab exercises, you will investigate each of these
extensions.
1) It enables new forms of instruction
profiling, by differentiating between instruction execution and commitment.
2) It estimates power consumption for
individual pipeline structures according to the Wattch framework.
3) It supports the concurrent execution of
multiple threads via the Simultaneous Multithreading (SMT) model.
4) It provides a cycle-accurate model for key
pipeline structures, which informs its SMT model.
M-Sim is light-weight, explicitly intended
for the Alpha AXP, a 64-bit RISC microprocessor. Therefore, at this time
all potential simulated programs must be compiled for the Alpha AXP
binaries. Though the Alpha has been
discontinued commercially [3], it remains an important subject of research,
informing proprietary product design.
The M-Sim tool set is a detailed timing simulator that supports
non-blocking caches, speculative execution, and state-of-the-art branch
prediction. In addition to its core simulator, the M-Sim package contains
statistical analysis resources, and debug and verification infrastructure,
using the DLite debugger.
What is
available in the M-Sim toolset?
The tool set consists of a single
microarchitecture simulator that emulates superscalar microprocessors at
different levels of detail. Invoked
as sim-outorder, it
is a precision timing
microarchitectural simulator. It supports the more complicated out-of-order
execution mode, and includes branch prediction, caches, and external memory.
This simulator is highly parameterized and many functional elements can be
modeled explicitly, as design considerations such as queue size and physical
size can be adjusted for such units as the issue queue (IQ) and per-thread
load/store queues (LSQ’s), and integer/floating point register files and
per-thread reorder buffers (ROB’s).
How does M-Sim
implement the SMT model?
M-Sim implements SMT by sharing some
processor structures between threads and leaving other structures private to
each thread. In particular, the IQ
and physical register files (integer and floating point) are shared between all
threads, while separate branch predictors, rename tables, LSQ’s, and ROB’s
are maintained. M-Sim only supports
independent processes with private memory spaces (dependent threads are left to
future work). For more information
see [4].
References:
1) http://www.cs.binghamton.edu/~jsharke/m-sim/
2) http://www.ecs.umass.edu/ece/koren/architecture/Simplescalar/
3) http://en.wikipedia.org/wiki/DEC_Alpha
4) http://www.cs.binghamton.edu/~jsharke/m-sim/documentation/msim_tr.pdf