This project determines the reliability of Interstitial Mesh Networks
through simulation. The simulation procedure implemented is described in
Estimating Reliability of Interstitial Mesh Networks.
Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for
Large Area VLSI processor Arrays by Adit D. Singh. The paper is a part
of IEEE Transactions on Computers, Vol. 37, No. 11, November 1988.
Java 1.4.2 is required for proper viewing of the applet. The Java environment
can be obtained from http://java.sun.com/j2se/1.4.2/download.html.