Concurrent Error Detection in ALU's by
Recomputing with Rotated Operands

This is a help for RESO (Re-computing with Shifted Operands) simulator. This simulator is created by using Java.
I tested this Java applet by using Internet Explore at Windows XP.

Introduction

From "Concurrent Error Detection in ALU's by Recomputing with Shifted Operands", Janak H. Patel and Leona Y. Fung.
 

 "One well-known time redundancy method is called "Re-computing with Shifted Operands by k-bit" (RESO-k). All operations are done twice, once with the normal operands, and once with the operands shifted by k bits. This method can detect k consecutive logic errors and (k-1) arithmetic errors; however, when an n-bit operand is shifted left by k bits, its leftmost k bits move out, To preserve these bits during the re-computation step, an (n+k)-bit Arithmetic Logic Unit (ALU) and several (n+k)-bit shifters are needed. Furthermore, since the length of the ALU has increased to (n+k) bits, the re-computation takes (n+k)-bit operations rather than n-bit operations. As k becomes larger, a considerable increase of space and time complexity occurs, and the error probability in the ALU increases also."

"Recomputing with Rotated Operands"(RERO) is one of methods of concurrent error detection. RERO was designed to overcome the limit of RESO. RERO re-computes rotated operand instead of shifted operand.  Here is a conceptual diagram of RERO.

During the first step, three rotators don't shift the data, therefore the input and output of rotator is same. During the second step, the first two left-rotator rotate input data by "K" bits and the right-rotator rotates input data by "K" bits.

The fault model used is the same model of RESO.
 

Usage

1. "Width of operand": Default value of this field is 16 bits. This means that input A or B value can be from 0x0000 to 0xFFFF.
2. "Rotate amount" : Default value of this field is 3 bits. This means that input A will be rotated by 3 bit. If A is 0x0001, shifted value will be 0x0008.
3. "Operation" : Default value of this field is OR. You can select OR, AND, NOT, and ADD.
4. "Operand A" & "Operand B": These are input values of this simulation.
5. "Faulty Bits(carry or out)" :By using this field, you can specify faulty bits. If you set "Faulty Bits(out)" as "0 1", this means that bit 0 and 1 is faulty and each bit can be stuck at High or Low.
6 "Generate Circuit" & "Step" : By using these buttons, you can run simulation.
7. "Clear Log": By using this button, you can clear the logs.

Theorems

RERO-k has the following error detection capabilities in an ALU:
1) detects (k mod n) consecutive bit errors for bit-wise logical operation where n is the length of the ALU,
2) detects (k-1) consecutive bit errors in a ripple carry adder when doing arithmetic operations.

Undetectable Fault Example

Width of operand:16
Rotate amounts:3
Operation: ADD
Operand A: 0xFFF0
Operand B: 0x0
Faulty bits(carry): 14 15 16
Faulty bits(out): 14 15 16


If you simulate these conditions, you may realize there are some undetectable faults. So I explained one undetectable fault example at here.

During un-shifted first stage, result should be 0xFFF0, but some combination of faulty situation will generate 0x3FF0.

	0	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0
+	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	0	1	1	1	1	1	1	1	1	1	1	1	1	0	0	0	0

This will be happen in this situation: The outputs of faulty bits are S14=0, S15=0, S16=0, C14=0, C15=0, C16=0.

During rotated second stage, result should be 0x1FF83, but some combination of faulty situation will generate 0x1FF84.

	0	0	1	1	1	1	1	1	1	1	1	1	1	1	0	1	1
+	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
	1	1	1	1	1	1	1	1	1	1	0	0	0	0	1	0	0

This will be happen in this situation: S14=1, S15=1, S16=1, C14=0, C15=0, C16=1. After right rotate, the result will be 0x3FF0. This means RERO-3 can't detect some fault in 3 bit faulty situation