Lab E2: Combinational Logic Design with Verilog HDL
Complete the following tasks using the Altera Quartus II software and Verilog HDL
Write Verilog code that implements a 4-bit ripple-carry adder. In addition to the four-bit Sum (S3,S2,S1,S0), your design should produce output C4 for carry generated in the most significant bit stage and an overflow bit V for use with signed numbers. You can use a structural (gate level) or a functional (data-flow) model of your Verilog code, as described in the course slides and in the textbook (Mano, Sections 3-10 and 4-12). Produce the gate level design and the block level diagram using RTL view o Quartus II.
Test your adder to demonstrate correct operation with the following additions of 4-bit signed
numbers in 2's complement representation:
- 0011 + 0010 (i.e., 3+2 in decimal)
- 0011 + 0110 (i.e., 3+6 in decimal)
- 0111 + 1010 (i.e., 7-6 in decimal)
- 1100 + 1011 (i.e., -4 -5 in decimal)
Show the correct result of these additions, clearly indicating the carry out bits and the value
of the overflow signal V. Compare them to the output values that your design actually generates.
Analyze your solution.
Lab Report
The lab report for Lab E2 is due Nov. 06, 2009 in class.
The lab report should contain:
- A print-out of your Verilog code.
- A printout of the schematics: include a block-level diagram of the top module and gate-level diagrams of the lower-level modules, generated by the RTL viewer of the Quartus tool.
- Simulation waveforms that exercise the circuit with the four additions shown above.
Show and thoroughly analyze your solution by comparing the outputs generated by your adder with the expected values.
The lab report for this assignment needs to adhere to the following guidelines:
- The report needs to be typed (i.e., not hand-written). Schematics, figures, tables, etc. should be computer-generated (unless permitted otherwise).
- The report should be paginated (all pages must have page numbers) and contain the following parts:
- Cover page (title, name, date, course number, etc.).
- Introduction: a brief description of the lab assignment in your own words (i.e., do not copy and past the assignment text from the web page)).
- Main body of report divided into properly named Sections, with detailed presentation of your work and analysis of results. Include all relevant material (print-outs of schematics, algebraic expressions and/or truth tables, whenever appropriate, etc.). Examples of section titles include:
Schematic entry, Verilog code, Truth tables, Simulation waveforms, Analysis of results, etc.
- Conclusions: briefly discuss your results and explain what you have observed and concluded from your experiments.
- Figures, tables, etc. should be labeled clearly. If possible, place them in the report such that is intuitively clear where they belong.
Resources
For references and examples of Verilog, consider the following links:
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