ENGIN112 - Introduction to Electrical and Computer Engineering

Lab E1: Creating and Simulating Gate-level Design Schematic

Part 1

Consider Boolean function F1 = x'yz + y'(x'z+x) for the Greenhouse Fan design (Lecture 9/10).

• Using Quartus II software, enter a gate-level schematic for function F1 using AND/OR logic gates and inverters as needed. How many gates do you need?
• Perform exhaustive functional simulation using Quartus II (make sure to set up simulation parameters for functional rather than timing simulation). Exhaustive simulation requires testing all possible input combinations. How many input combinations you must consider?
• Draw a truth table for F1 and compare it with the results from your simulation.

Part 2

Repeat the experiment for the minimized logic function F2 = x'z + xy' for the same Grrenhouse Fan design.

• Draw a gate-level schematic for F2 using the required logic gates. How many gates do you need now?
• Enter the gate-level schematic for F2 into Quartus II and perform exhaustive functional simulation using the same input stimulus file as in Part 1.
• Compare the results with Part 1.

What conclusions can you draw from this experiment?

Lab Report

The report must be typed (not hand-written). Hand-written reports will not be accepted. All schematics, figures, tables, etc. should be computer-generated. The report should be paginated (all pages must be numbered). It must contain a print-out or screenshot of both schematics and waveforms that show the simulation results for each part of the assignment. Make sure to provide Boolean expressions for F1 and F2 and show the corresponding truth table(s).

The report should contain the following parts:

• Cover page (title, your name, date, course number, semester/year, etc.).
• Introduction (brief description of the lab assignment in your own words (i.e., do not copy and past the assignment text from the web page)).
• Main body of report (with proper headlines) with detailed presentation of your work. Include all relevant material (print-outs of schematics, equations, truth tables, etc.). Figures, tables, etc. should be clearly labeled. Provide an adequate amount of text that explains the relevant steps of your work.
• Conclusions: discuss your results to explain what you have observed and concluded from your experiments.

Notes

Since you will be doing functional (rather than timing) simulation, make sure to correctly set the parameters of Quartus II software. Specifically:

• Use the command Generate Functional Simulation Netlist (from the Processing menu after design compilation. Remember that you have to recompile the design and generate the netlist every time you made a change to your design, prior to running the simulation.
• Set the simulation mode to Functional (from the Tools menu choose Simulator Tool and change the simulation mode accordingly).

For details, please refer to the following tutorials:

• Quartus II schematic capture & simulation tutorial.
• A complete Quartus II tutorial, including Verilog input and timinig simulation.