COURSE OUTLINE

  1. Introduction to Test Issues
    1. Terminologies
    2. Typical test flow
    3. Yield, DPM, Mortality, Economics
  2. Fault Modeling
    1. Stuck-at, Transition, Delay Faults,, Logical Redundancy
    2. Fault Equivalence, Fault Dominance
    3. Defect Based Testing
    4. IDDQ Testing
  3. Logic Simulation
    1. Compiled Simulation
    2. Event-Driven Simulation
    3. Delay Modeling
  4. Fault Simulation
    1. Parallel
    2. Deductive
    3. Concurrent
    4. Critical Path Tracing
    5. Fault Sampling
    6. Statistical Fault Analysis
  5. Combinational Test Generation
    1. Simulation Based
    2. D-algorithm
    3. PODEM  
    4. FAN  
    5. Testability based methods
  6. Sequential Test Generation
    1. Time-Frame Expansion  
  7. Design for Testability
    1. Overview - Test Problem Identification  
    2. Ad Hoc Insertion Technique
    3. Latch vs. FF based design
    4. Full Scan Design: MUX vs clocked scan
    5. LSSD Full Scan Design  
    6. Partial Scan Design  
  8. Built-In Self-Test
    1. Overview  
    2. Test Result Compression (MISR)  
    3. Pseudo-Random Pattern Generation (LFSR)  
    4. Pseudo-Exhaustive Testing  
    5. Pseudo-Random Testing  
    6. Pseudo-Random BIST Architectures
  9. Pattern Compression
    1. Compression
    2. Compaction  
  10. Memory Testing
    1. March Algorithm
  11.  Fault Diagnosis
    1. Dictionary Based
    2. Adaptive
  12. Advanced Topics
    1. Signal Integrity Issues