ECE 654

Testing is a critical aspect of the VLSI design cycle. Testing is also a dominant factor in IC manufacturing cost. As IC technology advances, designs become increasingly complex, making testing more challenging. To ensure high quality of test, a well-structured testing methodology is essential.

This course will discuss how ICs are tested after fabrication and after packaging. It will delve into strategies to minimize test application time and cost, all while ensuring the functional correctness of all tested ICs.

We will introduce the concept of fault model which guides the test pattern development process and discuss algorithms for test pattern generation for digital integrated circuits. We will also discuss complexity issues and how design-for-testability (DFT) is used to simplify the test generation problem. DFT is an indispensable part of VLSI design today.

This course aims to equip students with (i) fundamental test principles for digital integrated circuits, (ii) DFT architectures encompassing diverse self-test methodologies, (iii) test optimization techniques such as pattern compression, (iv) memory testing, and (v) methodologies for IC failure diagnosis.

Upon completing this course, students will be able to:

1. Understand Testing Needs
   Recognize the importance of systematic test methods for ensuring quality and reducing cost of complex IC Testing

2. Become familiar with Testing Methods
   Understand various testing methods in the manufacturing flow and system life cycle

3. Understand Test Generation and Design-for-Testability
   Learn test generation algorithms (e.g., PODEM) Understand scan design, boundary scan, built-in self-test, and similar DFT solutions

4. Become familiar with Advanced Testing Concepts
   Gain familiarity with delay testing, test compression, diagnosis, and 3D integration

5. Learn to apply fundamental test principles
   Apply course concepts to a term project