Csaba Andras Moritz Associate Professor 309H Knowles Engineering Bldg University of Massachusetts 151 Holdsworth Way Amherst MA 01003-9284 Telephone: (413) 545-2442 email: andras@ecs.umass.edu

M.S., Technical University, Cluj-Napoca, Transylvania, 1985
Ph.D., Royal Institute for Technology, Stockholm, Sweden, 1998.
1997-2000 Research Scientist at MIT

RESEARCH INTERESTS: Low power microprocessor design, single-chip multiprocessors, compilers and compiler-architecture interaction, computer architectures and circuits based on nanoelectronics, security in sensor networks.

AFFILIATED RESEARCH LABORATORY:
Software Systems & Architectures Laboratory

SELECTED RECENT PUBLICATIONS:

• Teng Wang, Mahmoud Ben-Naser, Yao Guo, Csaba Andras Moritz, Wire-Streaming Processors on 2-D Nanowire Fabrics, NSTI (Nano Science and Technology Institute) Nanotech 2005, California, May 2005.
• Raksit Ashok, Saurabh Chheda, Csaba Andras Moritz, Coupling Compiler-Enabled and Conventional Memory Accessing for Energy Efficiency, ACM Transactions on Computer Systems (TOCS), Vol 22, No. 2, pp. 180-213, May 2004.
• Osman S. Unsal, Raksit Ashok, Israel Koren, C. Mani Krishna, Csaba Andras Moritz, Cool-Cache: A compiler-enabled energy efficient data caching framework for embedded/multimedia processors, ACM Transactions in Embedded Computing Systems (TECS), Special issue on power-aware embedded computing, Vol. 2, No. 3, pp. 373-392, Aug 2003.
• Csaba Andras Moritz, Donald Yeung, Anant Agarwal, SimpleFit: a Framework for Analyzing Design Tradeoffs in Raw Architectures, IEEE Transactions on Parallel and Distributed Systems, Volume 12, Number 7, pp. 730-742, July 2001.

SOCIETY MEMBERSHIPS: ACM, IEEE.

HONORS & AWARDS: Two issued patents, two pending. 7 NSF awards (CCR, ITR, NER, SBIRs) as PI and 1 DARPA as co-PI. European Community TRACS (Training and Research in Advanced Computer Systems) Fellowship.

INSTITUTIONAL & PROFESSIONAL SERVICE: Associate Editor of IEEE Transactions on Computers. Co-chair of and organizer of Boston Area Computer Architecture Workshops: BARC2004 and BARC2005., Reviewer for: International Symposium on Computer Architecture, International Symposium on Architecture Support for Programming Languages and Operating Systems, IEEE Transactions on Parallel and Distributed Systems, Journal of Parallel and Distributed Computing. Department service: PhD comprehensive exams advisory committee.

 

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