Sandip Kundu Professor 309J Knowles Engineering Bldg University of Massachusetts 151 Holdsworth Way Amherst MA 01003-9284 Telephone: (413) 577-3309 email: kundu@ecs.umass.edu

B. Tech. Electronics & Elec. Comm. Eng., Indian Institute of Technology, 1984;
Ph.D., University of Iowa, 1988.

RESEARCH INTERESTS: VLSI Circuit Design & Test, CAD for VLSI circuit Design & Test, Design & Testing of highly scaled circuits, Design of Resilient Computing Systems.

SELECTED RECENT PUBLICATIONS:

• "Sandip Kundu, Sujit Zachariah, Yi-Shing Chang, Chandra Tirumurti, “On modeling interconnect crosstalk faults”, Accepted IEEE Transactions on CAD 2005.
• "Sandip Kundu, “Pitfalls of Hierarchical Fault Simulation”, IEEE Transactions on CAD, February 2004, pp. 312- 314.
• "C. Tirumurti, S. Kundu, S. Sur-Kolay, “Analysis and Modeling of Power Supply Grid”, Design Automation and Test in Europe Conference, 2004.
• "Sandip Kundu, T. M. Mak, Rajesh Galivanche, “Trends in manufacturing test methods and their implications”, International Test Conference 2004.

BEST PAPER AWARDS:

• The Best of ICCAD – 20 Years of Excellence in Computer Aided Design
  S. Kundu, S. M. Reddy and N. Jha, “On The Design of Robust Multiple Fault Testable CMOS Combinational Logic Circuits” IEEE International Conference on Computer Aided Design, Santa Clara, November 1988).
• S. Kundu and S. M. Reddy, “Design of TSC checkers for implementation in CMOS technology,” Int. Conference on Computer Design, Boston, October 2-4, 1989.

SELECTED PATENTS:

• On Weighted Random Pattern Self-Test Hardware. US Patent No: 5,297,151.
• A CMOS transistor network to gate level model extractor for simulation, verification and test generation, US Patent No: 5,629,858.
• System and method for testing internal nodes of an integrated circuit at any predetermined machine cycle, US Patent No: 5,793,777.
• Technique for sorting high frequency integrated circuits, US Patent No: 5,796,751.
• Constrained Signature-Based Test, US Patent No: 6,510,398.
• System for rearranging plurality of memory storage elements in a computer process to different configuration upon entry into a low power mode of operation, US Patent No: 6,715,091.

SOCIETY MEMBERSHIPS: IEEE.

INSTITUTIONAL & PROFESSIONAL SERVICE: Associate Editor of IEEE Transactions on Computers, General Chair: ICCD (2001), VLSI (2005), Technical Program Committee Member of several IEEE sponsored conferences, Keynote speaker at DCIS (2000), GMM Workshop (2000, 2005).

 

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