Maciej J. Ciesielski Professor 309B Knowles Engineering Bldg University of Massachusetts 151 Holdsworth Way Amherst MA 01003-9284 Telephone: (413) 545-0401 email: ciesiel@ecs.umass.edu

M.S., Warsaw Technical University, 1974; Ph.D., University of Rochester, 1984.

RESEARCH INTERESTS: Computer-aided design of VLSI circuits and systems. Behavioral and RTL synthesis. Formal verification and design validation. Layout synthesis.

AFFILIATED RESEARCH LABORATORY:
VLSI CAD

SELECTED RECENT PUBLICATIONS:

• M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, "Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification", Design Automation and Test Conference, DATE-2002, pp. 285-289, March 2002.
• C. Yang, M. Ciesielski, "BDS: A BDD-based Logic Optimization System", IEEE Trans. on Computer-Aided Design, Vol.21, No.7, pp 866-876, July 2002.
• M. Ciesielski, S. Askar, S. Levitin, "Analytical Approach to Layout Generation of Datapath Cells", IEEE Trans. on Computer-Aided Design, Vol. 21, No. 12, pp. 1480-1488, Dec. 2002.
• M. Fujita, Y. Matsunaga, M. Ciesielski, "Multi-Level Logic Optimization", in Logic Synthesis and Verification, Kluwer Academic Publishers, ed. by T. Sasao and S. Hassoun. Chapter 2, pp. 29-67, Aug. 2001.
• Z. Zeng, P. Kalla, M. Ciesielski, "LPSAT: A Unified Approach to RTL-Satisfiability", Design Automation and Test in Europe Conference, DATE-2001, pp. 398-402, March 2001.

SOCIETY MEMBERSHIPS: IEEE, senior member; ACM member

INSTITUTIONAL & PROFESSIONAL SERVICE: Technical Program Committees: VLSI 2001, 1999, 1997; ICCAD 1992, 1993; IWLS 1991, 1993; conference session chairman. Invited tutorials: ISCAS 1989, 1994; Digital Equipment Corporation; GE. NSF proposal review panel, member; reviewer for IEEE Transactions. Developed a new course for freshmen engineering, ECE 112.

 

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