Tutorial Sessions will be held at the same venue, on Sunday, November 20, 2011.

Tutorial 1: Delay Test for High-Performance Designs
Srinivas Patil, Intel Corporation(USA) and Sreejit Chakravarty, LSI Corporation(USA)

Tutorial Summary:
Today's nanometer designs continue pushing the performance envelope under the constraints of power and area. The combination of smaller design margins, and the inherent process variability requires addressing defects beyond static defects, particularly delay defects. The goal of this tutorial is to address testing for delay defects in a comprehensive yet practical fashion. The tutorial will start with a general introduction to delay defects, followed by a discussion of various fault models used to model them. This will be followed by a discussion of various testing techniques needed to target delay faults, including the DFT support needed in the design. We will discuss various techniques needed to improve the efficacy of delay testing, including metrics beyond gross fault coverage to measure their effectiveness, inclusion of timing information to target critical paths, accounting of environmental conditions such as cross-talk and power droop, utilization of hardware compression techniques to reduce delay test cost, and diagnosis techniques needed to pin-point delay test failures for failure analysis and yield enhancement. Throughout the tutorial, we will use real-world examples of delay test implementation based upon representative industrial test cases. Though the tutorial focus is on the concepts behind delay testing rather than particular EDA tools which enable automation, we will mention generic tool capabilities where appropriate.

The intended audience for this tutorial is practicing engineers (Design, DFT, Product Test, Reliability, Design Automation), Design and DFT Managers, students and academicians. The goal is to leverage from more than 25 years research and industrial practice in the delay test area, to present an overview of theoretical and practical aspects of delay test. At the end of this tutorial, the attendees should be able to gain a broad overview of this area, along with an understanding of relevance and applicability to their own environment. There are no pre-requisites for this tutorial: the tutorial will build from the basics to advanced concepts, and will be appropriate for those who are new to this area, as well as those who want to delve into the more advanced concepts of delay testing and fine-tune their existing methodology.

Tutorial 2: Scan Compression Techniques: Theory and Practice
Rohit Kapur, Synopsys, Inc.(USA); Nagesh Tamarapalli, AMD (India); Arvind Jain, Texas Instruments (India) and Rubin Parekhji, Texas Instruments (India)

Tutorial Summary:
Large designs, larger test pattern volumes and longer test times have necessitated the use of test data volume and test time compression techniques built around the scan design paradigm. The adoption of these techniques is increasing. Much as well as they are understood today, these techniques continue to present challenges in their adoption and implementation. As their adoption increases, new compression targets are set, in turn forcing the investigation of better solutions and upper bounds.
This tutorial will provide a comprehensive coverage of scan compression. It will begin with cost models to help designers understand the choices available to them. Mathematical formulations for different compression techniques and their influence on test pattern generation will be presented. Implementation techniques and tradeoffs will be described through various examples derived from IP (intellectual property) cores and large chips. Diagnostics, which is an important part of deep sub-micron designs, will also be discussed within the realm of compression, together with techniques which improve diagnosability. Emerging developments in this technology will be described. Finally, compression results from case studies involving different flavours of IPs and SOCs will be presented to illustrate how best the theory and practice fit together.

The attendees will appreciate the nuances of scan compression, various tradeoffs in their adoption, and entitlement gaps better, and gather additional insight into what promises can be made in terms of practical bounds, compression friendly designs, the (non-)tolerance to Xs, and pattern optimisations. They will also appreciate from the implementation viewpoint the duality between test data volume and test time (test cycles), modular compression architectures for large SOCs (system-on-chips), and the design space between traditional ATPG and classical logic BIST.