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ATS 20th Anniversary Compendium of Papers
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About this conference

20th ATS 2011 is the twentieth in this series of symposia started in 1992 devoted to testing, fault tolerant computing and the design of reliable circuits and systems. ATS is recognized as the main event in Asia that covers the many dimensions of testing and fault-tolerance. In 2011, the 20th Anniversary of the Asian Test Symposium will be celebrated in New Delhi, India and is of particular sinificance due to the rise of Asia, over the last several decades, in the areas of integrated circuit design and manufacturing, and electronic systems and software engineering, both of which embrace testing as a core technology. New Delhi, in particular, is a major player in India's computing industry with emerging "technology satellites" in nearby Noida and Gurgaon and the face of her new "modernity". At the same time, New Delhi, is the centerpiece of Indian culture, tradition and cuisine, having been at the helm of Indian history for centuries, dating back to the Mughal period and the British Raj.

Symposium Theme

The theme for ATS 2011 will be "Test Odyssey 2020: Testing Systems and Devices at the Peta and Nano Scales". This theme is inspired by the fact that technology is trending towards extremely high levels of integration at the package and chip levels, very high speeds of operation (> 100 GHz) and use of deeply scaled technology (approaching 10nm CMOS). In addition, a key test challenge will arise due to the ability to design complex systems such as robots that encompass sensors, communications systems, processors, transducers and enabling software. In addition to passing post-manufacture test procedures, such systems and relevant devices must exhibit fault-tolerance and survivability characteristics.

Topics of Interest (but are not limited to)

Original contributions in testing, fault tolerant and reliable computing are solicited. Topics of interest include, but are not limited to, the following categories:

Automatic Test Pattern Generation (ATPG) Boundary Scan
Test Compression Online Test
Temperature/Power-aware Test Design-for-testability (DFT)
Microprocessor Test Mixed signal and Analog Test
Memory Test System-in-package (SiP)/ 3D Test
Test Quality and Reliability Design Validation/Silicon Debug
Fault Modeling/Defect Based Test Fault Simulation/Diagnosis
Software Testing Board and System Test
Other

Important Dates/Deadlines

Papers May 27 June 10, 2011
Special Session proposals June 3 June 17, 2011
Tutorial proposals June 3 June 17, 2011
Exhibition/Booth proposals May 27 June 10, 2011
Notification of acceptance August 1 August 15, 2011
Camera-ready paper due date August 22 September 5 September 20, 2011