14th IEEE Symposium on Computer Arithmetic

Adelaide, Australia

April 14 - 16, 1999


Tuesday April 13 at 6pm: Reception at the town hall hosted by the Lord Mayor of Adelaide.

  Wednesday, April 14 Thursday, April 15 Friday, April 16
9:00-10:40 Opening Remarks
Invited Talk
Processor Enhancements
Divide and
Square Root
Rounding and
10:40-11:00 Coffee Break Coffee Break Coffee Break
11:00-12:15 Addition Number Systems Floating Point
12:15-14:00 Lunch Lunch Closing Remarks
14:00-15:15 Division Residue Systems Excursion
15:15-15:45 Coffee Break Coffee Break  
15:45-17:00 Cryptography and Graphics Cordic Algorithms  
17:15-18:00 Panel Session    
18:30-   Conference Banquet  


Wednesday, April 14

9:00-9:05 Opening Remarks, Jean-Michel Muller and Neil Burgess

9:05-9:50 Invited Talk, Chair: Israel Koren

Computer Arithmetic - A Programmer's Perspective
Richard P. Brent - Computing Laboratory, Oxford University, UK
(PostScript version) (PDF version)

9:50-10:40 Processor Enhancements, Chair: Peter Kornerup

New Algorithms for Improved Transcendental Functions on IA-64
S. Story and P.T.P Tang - Intel Corporation
(PostScript version) (PDF version)

A Low-power, High-speed Implementation of a PowerPC Microprocessor Vector Extension
M. Schmookler, M. Putrino, A. Mather, J. Tyler, H.V. Nguyen, C. Roth, M. Sharma, M. Pham and J. Lent - IBM Corporation, Austin, TX
(PostScript version) (PDF version)

11:00-12:15 Addition, Chair: Neil Weste

Intermediate Variable Encodings that Enable Multiplexor-based Implementations of Two Operand Addition
D. Phatak and I. Koren - SUNY, Binghamton and UMass, Amherst
(PostScript version) (PDF version)

A Family of Adders
S. Knowles - Element 14, UK
(PostScript version) (PDF version)

Reduced Latency IEEE Floating-Point Standard Adder Architectures
A. Beaumont-Smith, N. Burgess, S. Lefrere and C. Lim - The University of Adelaide, Australia
(PostScript version) (PDF version)

14:00-15:15 Division, Chair: Renato Stefanelli

On the Design of High-Radix Online Division for Long Precision
A. Tenca and M. Ercegovac - Oregon State University and UCLA
(PostScript version) (PDF version)

Boosting Very High Radix Division with Prescaling and Selection by Rounding
P. Montuschi and T. Lang - Politecnico di Torino and UC Irvine
(PostScript version) (PDF version)

Low-Power Division: Comparison Between Implementations of Radix 4, 8 and 16
A. Nannarelli and T. Lang - UC, Irvine
(PostScript version) (PDF version)

15:45-17:00 Cryptography and Graphics, Chair: Milos Ercegovac

Montgomery Modular Exponentiation on Reconfigurable Hardware
T. Blum and C. Paar - Worcester Polytechnic Institute, MA
(PostScript version) (PDF version)

Moduli for Testing Implementations of the RSA Cryptosystem
C. Walter - UMIST Manchester, UK
(PostScript version) (PDF version)

Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3D Vector
N. Takagi and S. Kuwahara - Nagoya University, Japan
(PostScript version) (PDF version)

17:15-18:00 Panel Session

Title and panel to be determined

Thursday, April 15

9:00-10:40 Divide and Square Root, Chair: Atsuki Inoue

Correctness Proofs for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms
M. Cornea-Hasegan, R. Golliver and P. Markstein - Intel and Hewlett-Packard Corporation
(PostScript version) (PDF version)

Floating Point Division and Square Root Algorithms and Implementation in the AMDK7 Microprocessor
S. Oberman - Advanced Micro Devices, CA
(PostScript version) (PDF version)

Series Approximation Methods for Divide and Square Root in the Power3 Processor
R. Agarwal, F. Gustavson and M. Schmookler - IBM Corporation, Austin, TX
(PostScript version) (PDF version)

High-Speed Inverse Square Roots
M. Schulte and K. Wires - Lehigh University, PA
(PostScript version) (PDF version)

11:00-12:15 Number Systems, Chair: Colin Walter

Arithmetic with Signed Analog Digits
A. Saed, M. Ahmadi and G. Jullien - Nortel Semiconductors and University of Windsor, Canada
(PostScript version) (PDF version)

A 32Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point
J. Coleman and E. Chester - University of Newcastle, UK

Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition
P. Kornerup - Odense University, Denmark
(PostScript version) (PDF version)

14:00-15:15 Residue Number Systems, Chair: Graham Jullien

Efficient VLSI Implementation of Modulo (2^ną1) Addition and Multiplication
R. Zimmermann - ETH Zurich, Switzerland
(PostScript version) (PDF version)

A Reverse Converter for the 4-Moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}
M. Bhardwaj, T. Srikanthan and C. Clarke - Siemens Components, Singapore.
(PostScript version) (PDF version)

VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspective
M. Bhardwaj, T. Srikanthan and C. Clarke - Siemens Components, Singapore.
(PostScript version) (PDF version)

15:45-17:00 CORDIC Algorithms, Chair: Jeong Lee

Interval Sine and Cosine Functions Computation Based on Variable Precision CORDIC Algorithm
J. Hormigo, J. Villalba and E. Zapata - University of Malaga, Spain
(PostScript version) (PDF version)

Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms
D. Lewis - University of Toronto, Canada
(PostScript version) (PDF version)

Very High Radix CORDIC Vectoring with Scalings and Selection by Rounding
E. Antelo T. Lang and J. Bruguera - University of Santiago de Compostela, Spain and UC Irvine
(PostScript version) (PDF version)

Friday, April 16

9:00-10:40 Multiplication and Rounding, Chair: William McAllister

Area x Delay (AT) Efficient Multipliers Based on an Intermediate Hybrid Signed Digit Representation
J. Lue and D. Phatak - Summit Systems and SUNY, Binghamton, NY

A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication
G. Even and P. Seidel - Tel-Aviv University, Israel and Univ. Saarbruecken, Germany
(PostScript version) (PDF version)

On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal
C. Iordache and D. Matula - Southern Methodist University, Dallas, TX
(PostScript version) (PDF version)

Number-Theoretic Test Generation for Directed Rounding
M. Parks - Sun Microsystem, CA
(PostScript version) (PDF version)

11:00-12:15 Floating Point, Chair: Stuart Oberman

Multiplications of Floating Point Expansions
M. Daumas - Ecole Normale Superieure de Lyon, France
(PostScript version) (PDF version)

The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures
E. Schwarz, R. Smith and C. Krygowski - IBM Corporation, Poughkeepsie, NY
(PostScript version) (PDF version)

Floating Point Unit in Standard Cell Design with 116 bit Wide Dataflow
G. Gerwig and M. Kroener - IBM Corporation, Poughkeepsie, NY
(PostScript version) (PDF version)

12:15-12:30 Closing Remarks

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Last modified: Jan. 27, 1999