Department of Electrical and Computer Engineering                      University of Massachusetts Amherst

ECE 697EE - Fall 2005 

Nano Computing

(Architect's view on nanoelectronics based systems)

InstructorCsaba Andras Moritz, Professor
email: andras@ecs.umass.edu, phone: 413-545-2442
Office: room KEB-309H

Secretary:   Chris Langlois, phone: 413-545 3621
Office hours: by appointment
Class Time: TuTh from 9:30AM

Place:  Knowles 3-rd floor conference room (please note location has changed; it is NOT Lederle A201)
NOTE: Research papers and other materials are distributed in class or posted on this page.



Course Abstract:

Nanoelectronics based systems promise orders of magnitude higher densities than CMOS at the end of the silicon roadmap. Device technologies based on Silicon Nanowires (SiNW) and carbon nanotubes (CNT), structures that are just a few nanometers,  are successfully  shown to exhibit diode- and FET-like behavior.  Much additional progress has been made in forming arrays with such switching elements and on required manufacturing steps. These include  nano-litography, chemical self-assembly, and CMOS-nano interfacing techniques. Similarly, there are several directions explored for nano-micro interfacing and wiring.  Several challenges and questions remain unanswered when building larger scale designs. Would systems built out of such devices outperform CMOS? What would be the density at the system level? Would there be significant speed, performance, and power advantages?

This course is a seminar course and will be discussing various ways of using CNT and SiNW based devices to build computing systems (and building blocks for nanoscale systems). We will study research papers ranging from nanoscale architecture (like WISP, NASIC, CMOL, nanoPLA), fault tolerance approaches proposed (both based on defect map availability and proposals without defect maps), circuit layers (pla, static and dynamic NASICs, hybrid approaches with CMOS), micro-nano interfacing (decoder imprint, stochastic approaches with differentiated nanowires, CMOS pin array, etc ) and manufacturing issues (what can and cannot be done). While all layers will be addressed in this course (necessary in order to understand the "big picture"), the focus will be on the architecture/implementation layers and circuit issues.   We will follow a top-down approach: a number of proposals for nanoscale systems are first discussed at high level before delving into implementation and device challenges.      
(3 credits)


Projects/Exams/Grading:
This is a research oriented seminar course and requires full participation. Its focus is to prepare students to do research in this area. Students are expected to give one  30 minutes presentation of research papers (selected by the instructor) and to participate actively in informal (brainstorming style) research discussions. Projects will be listed below. Each student is required to write one "wild idea" paper ( not more than four pages) related to one promising technique/idea he/she comes up with.  One exam. Grading: 10% class attendance, 10% presentation, 50% projects, 30% final exam (material will be selected by instructor).

Prerequisites: Desire to understand capabilities of nanoscale systems.  Good (e.g., undergraduate level) knowledge of computer architecture, circuits, and some understanding of compiler and VLSI implementation issues in microprocessors.

Materials from:


Suggested list of material to read and topics discussed in class - list will be updated as we go along... See below a preliminary schedule.

Lecture 1: Introduction to nano scale devices (NWs and CNTs). Discussion in class about directions for nanoscale systems.

Lecture 2-3-4: Circuit-Architecture-Compiler layers:  Csaba Andras Moritz, NASIC/WISP project overview [ppt].
Static NASICs, Dynamic NASICs, WISP-0, Fault Tolerance.

Additional Reading:
- Teng Wang, Mahmoud Ben-Naser, Yao Guo, Csaba Andras Moritz, Wire-Streaming Processors on 2-D Nanowire Fabrics, NSTI (Nano Science and Technology Institute) Nanotech 2005, California, May 2005. [Extended Version].
- Csaba Andras Moritz, Teng Wang, Latching on the Wire and Pipelining in Nanoscale Designs, 3rd Workshop on Non-Silicon Computation (NSC-3), ISCA'04, Germany, Jun 2004. [PDF]

Lecture 5: Circuit-Architecture-CAD: NASIC/WISP/Madeo tools overview. Presenter Teng Wang.

Reading:
- NASIC Madeo presentation
- Teng Wang, Mahmoud Ben-Naser, Yao Guo, Csaba Andras Moritz, Wire-Streaming Processors on 2-D Nanowire Fabrics, NSTI (Nano Science and Technology Institute) Nanotech 2005, California, May 2005. [Extended Version].
- Csaba Andras Moritz, Teng Wang, Latching on the Wire and Pipelining in Nanoscale Designs, 3rd Workshop on Non-Silicon Computation (NSC-3), ISCA'04, Germany, Jun 2004. [PDF].
- Teng Wang, Zhenghua Qi, Csaba Andras Moritz, Opportunities and Challenges in Application-Tuned Circuits and Architectures Based on Nanodevices, Proceedings of the First Conference on Computing Frontiers, pp. 503 - 511, Italy, Apr 2004. [PDF]

Lecture 6: Circuit-Architecture: CMOL; Panel by Dan, Teng, and Sheng. Moderator: Moritz. Presentations: Teng's, Sheng's, and Dan's

Reading:
 -X Ma, et al, "Afterlife for Silicon: CMOL Circuit Architectures";
- K Likharev et al, "CMOL: Devices, Circuits, and Architectures".

Lecture 7: Circuit-Architecture layer: CMOL,

Reading: see above

Lecture 8: Circuit-Architecture layer:  nanoPLA style of approaches resembling a PLA

Reading:
- A Dehon, "Design of Programmable Interconnect for Sublitographic Programmable Logic Arrays"
- A Dehon: Array-Based Architecture for FET-Based Nanoscale Electronics
 

Lecture 9 Circuit-Architecture layer:  nanoPLA  Presentations by Yao, Mike, and Mahmoud

Reading:
- A Dehon, "Design of Programmable Interconnect for Sublitographic Programmable Logic Arrays"
- A Dehon: Array-Based Architecture for FET-Based Nanoscale Electronics

Lecture 10: Circuit-Architecture layer: nanoFabrics. Presentations by Ibis and Chang

Lecture 11: nanoFabrics

Lecture 12: DNA Self-Assembly approaches. Use DNA hybridization as a way to assemble 2-D and 3-D circuits.

- Chris Dwyer et al, Duke. Chapter 3 in PhD thesis. Jon's presentation.

Lecture 13: How to build semiconductor and conductor hetero-structures . Presentation.

- Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures, Yeu Wu et al
- Doping and Electrical Transport in Silicon Nanowires, Yi Cui, et al
- Growth and transport properties of complementary germanium nanowire field-effect transistors

Lecture 14: Modulation based NW FETs. Addressing without lithography.

- Zhong et al, "Nanowire Crossbar Arrays as Address Decoders for Integrated Nanosystems", Science 302, 1377, 2003
- Dehon et al, "Stochastic Assembly of Sublithographic Nanoscale Interfaces", IEEE Transaction on Nanotechnology, 2003

Lecture 15

- S Goldstein, "The Impact of the Nanoscale on Computing Systems"

Lecture 16

- M.B. Tahoori, "A Mapping Algorithm for Defect-Tolerance of Reconfigurable Nano-Architectures" Ibis's presentation

Lectures 17-19

- Byron D Gates, et al. "Unconventional manufacturing", Annual Review Material Research 2004, 34:339-72. Presentations by Dan and Shang

Lecture 20

- Review of second project results.

....

FINAL Exam: December 20, Tuesday at 1PM, Place Knowles 3-rd floor conference room. Material: all papers discussed in class. Papers about manufacturing techniques and devices are allowed at the exam. Students preparing a wild idea paper (deadline December 22, at 11AM) do not have to take the exam.


Mini-project 1: Comparison between NASIC, CMOL and nanoPLA. Groups of 2-3 students.
Take a WISP block and develop corresponding circuit with nanoPLA and CMOL approaches. Compare density for the three approaches. Propose improvements.

Initial phase: deadline Oct 18. This is a comparison between the CMOL and NASIC 1-bit adder

Next phase: deadline November 1. Complement with comparison with nanoPLA.

Requirements: (i) a research report shortly describing your work and results, and (ii) oral defense where questions related to the goals outlined and your results will be asked. Deadline November 29.

Mini-project 2.  NASIC Circuit-Level Work. Groups of 2-3 students.
Estimate the retention time of the output due to static currents in the nano latch NASIC circuit. Look at DRAM for inspiration. Propose methods to keep output. Explore solution for the fault tolerant version of the NASIC dynamic circuit.

Requirements: (i) a research report shortly describing your work and results, and (ii) oral defense where questions related to the goals outlined and your simulation will be asked. Deadline November 29.

Alternative: CMOL circuits for ROM, Decoder, etc. Comparison with NASIC version. Deadline TBD.

Mini-project 3 and 4: Tools and Fault Tolerance and Performance Models. Groups of 2-3 students. This project is optional.

Requirements: (i) a research report shortly describing your work and results, and (ii) oral defense where questions related to the goals outlined and your simulation will be asked. Deadline is TBD.

Q1: Incorporate dual redundancy fault tolerance technique  into Madeo's mapping for WISP designs.

Q2: Develop version of Madeo for mapping to CMOL

Q3: Abstract Performance Simulation with Mathematica of NASICs, CMOS and nanoPLA

Wild idea paper: your short paper on a nanoscale design.  Will be evaluated based on similar criteria used in conferences (1. Innovation, 2. Organization/language, 3. Evaluation methodology and arguments used to convince reader about feasibility of the idea). Should state the problem, compare with state-of-the-art, cite related work, argue for why it would work and also possible problems you expect (you can use back-of-the-envelope type of reasoning). Deadline Dec 22, 11AM. Private discussions Dec 2. For other appointments please send email. [Guide]

 



Last updated:12/13/2005
andras@ecs.umass.edu