Project Instructions

Document preparation:

1. Use preferably LATEX to construct your document. If you haven't done this before I can give you a template (send me email) and point you to more resources.
2. Create a postscript and a PDF document from your files. You need to write a Makefile to automate this process.
3. Partition the paper into several sections each put in a separate file.
4. Components:
    - title
    - Abstract -- 15 second version of the paper
    - Introduction - background and give motivation
    - Multiple sections about the idea proposed and solution provided
    - Describe experimental Methodology used (e.g., simulation, analytical etc..) and provide Results    
    - Conclusions - Has the idea worked?

5. email your paper, including all files/experiments, in tar format (use "tar -cvf classECE697E-yourname.tar *  ")  to me before the deadline from the schedule page. Check with me regularly to make sure that you are on the right track regarding the content of your paper.
6. email the ps and/or pdf files separately.
 

 

Research Topics

Please note, this is speculative research, so what you do is free to some extent.  The objective is to train "doing research" with my help. I will act more as an advisor. You will see how difficult it is, when not only you have to come up with solutions to hard problems but also need to define the problem.  Both of these proposals below are open research problems.

A. Fine-grained synchronization in multiprocessors and parallel systems-on-a-chip [project overview]. The idea is to combine synchronization and cache-coherence in a full/empty bit memory system architecture. Fine-grained synchronization helps preserve the parallelism in the application. Detailed project description about some of the concepts and initial thinking will be provided to you. The project requires the design of one scheme and evaluation of it with the RSIM simulator. As baseline the MIT-Alewife architecture should be used. Cool idea would be to extend this project to speculation between threads, i.e., use same hardware(or with minor modification) to support speculation, coherence, and fine-grained synchronization within the same framework. Alternatively, new ideas well argued for in within this topic are also acceptable. This project can be chosen by 2 groups, each with 2-3 students.

B. Short-range connectivity for tiled billion transistor architectures. This project idea is based on a recent "idea" paper, called Short Range Connectivity for Tiled Architectures, that is available from the SSA group's webpage (you will find this from my research group's web page /ece/andras/SSA/ssa4, [Postscript] ). The idea is to have a wireless short-range network to supplement existing interconnection networks on large configurations with thousands of processors. We believe that a few well-placed Bluetooth (BT) tiles would considerably improve performance by reducing network contention on the wired networks. There are several possible research directions. (1), to integrate/study how a Bluetooth simulator, that we have from IBM, can be integrated with an execution driven simulator of hybrid (BT + tiled) architectures and possibly experiment with it to gain insights about possibilities. Using the BT simulator would also help us understand the performance aspects of BT. (2) some of the algorithms used in BT should be tried to be rewritten/reformulated in a parallel fashion, so that the algorithm can be implemented in software rather than hardware. (3), using SimpleFit (see papers SSA site) and its Mathematica implementation (you need to have access to Mathematica on either PC or Unix), experiment with designs that incorporate BT tiles. Question is: will these designs change significantly with the addition of BT tiles? The ultimate research goal would be to come up with a simplified version of BT that has much lower overhead is shorter-range (centimeters instead of meters), and more applicable for parallel chips. This project can be chosen by 2 groups, each with 2-3 students max.

On-campus groups can meet with me bi-weekly for brainstorming/research sessions. Off-campus students can send me email or talk to me on the phone. If you are off-campus, you work alone, and would prefer something more predictable, please send me an email to available discuss options.

This is research, so please be brave and think out-of-the-box!

Example of other paper ideas (you are welcome to propose your own idea):

1. Analytical comparison between Raw and Vector Iram

Based on the SimpleFit and the IRAM papers design and implement a model to
compare the performance of a Raw processor and an IRAM chip using vector
microprocessors. Use the SimpleFit simulation model for Raw and extend it for IRAM chips.
Assume one billion transistor architectures. (groups of max 2)

2. Analytical comparison between Raw and FPGAs

Model and compare FPGAs with a Raw chip. Use and extend the SimpleFit simulator. Assume one billion transistor architectures. (2 people)

3. Evaluate cost-performance-power efficient designs for next generation parallel architectures on a chip. You need to modify SimpleFit with a power model.


andras@ecs.umass.edu , 01/05/2002 {back to main page}