Department of Electrical and Computer Engineering University of Massachusetts Amherst
ECE 668 - Spring 2009
Computer Architecture
Instructor: Csaba Andras Moritz, Professor
email: andras@ecs.umass.edu, phone: 413-545-2442
Office: room KEB-309H
Secretary: Christine Langlois, phone: 413-545 3621
Office hours: Tue-Th 1PM-2PM
Class Time: Tue-Th from 11:15AM-12:30PM
Place: Marston Hall Room 15
NOTE: Research papers and other materials are either distributed in class or posted on this page.
Course Abstract: This course will cover advanced topics in computer architectures focusing on emerging uniprocessor and multiprocessor architectures, implementation issues (architect's perspective) in deep submicron CMOS, and nanoscale architectures based on new types of devices. Outline: (1) Introduction; (2) Reminder on Pipelined Processors; (3) Parallelism and ILP; (4) Memory Hierarchy Design (caches, virtual memory); (5) Multiprocessors (shared memory, distributed memory, synchronization, etc); (6) Implementation Issues in Deep Submicron (power, process variation, etc); (7) Nanoscale Computer Architecture. (3 credits)
This is a core graduate level course. Active student participation is expected. The course will have one or two projects, one midterm and a final exam. Projects will be listed below. Grading: 10% class participation, 40% projects, 20% midterm, 30% final exam, and 0% homeworks.
Prerequisites: If you are taking this course you must have already taken an undergraduate level architecture course and have basic understanding of computer organization and microprocessor architecture. The projects require good command of programming in either C, C++, C#, Java or Verilog. Projects are individual.
Materials from:
- research papers - will be listed in class
- [1] Hennesy and Patterson, Computer Architecture A Quantitative Approach, 4th Edition - this is the main textbook for the class
- [2] J. P. Shen and Mikko H. Lipasti, Modern Processor Design
Other useful books to have:
- [1] Chandrakasan et al, Design of High-Performance Microprocessor Circuits
- [2] Jan M. Rabaey, Digital Integrated Circuits
Project: Project Description. DUE THURSDAY MAY 8, CLASS TIME and AFTER, TBD, in Knowles 309H. Sign up at http://www.mysignup.com/ece668project
Project help/instructions from the TA, Mid Project Review tbd, Final Project Deadline/Review. gcc-2.7.2.3 .
Midterm: April 7, 2009; regular classroom, 1 hour, Midterm Review
Final Exam: E&C-ENG 668 TBD, Marston Hall 211, Final Review.
Slides/Papers: Introduction, Pipelines (updated from last week with power related slides), Dynamic and Power-Aware Branch Prediction, (see document with TA's instructions for the project above), Dynamic Scheduling, ARM Architecture Paper (ARM Reference Manual), Exceptions, ROB, & Speculative Tomasulo, ROB Paper, Multiple Issue, Limits for ILP, Midterm Review, Multi-core, Compiler-managed ILP(2), Midterm Exam, Individual Project Review, Software and Hardware-Based Prefetching (performance and power-aware) (2), Process Variation Resilient Architectures, Virtual Memory, Nanoscale Processors & NASICs (2), Overview Multiprocessors (if we have time), Final Exam Review (TBD), Final Project Review (TBD).
Last updated: January 15, 2009
andras@ecs.umass.edu