Department of Electrical and Computer Engineering University of Massachusetts Amherst
ECE 668 - Spring 2016 - Welcome
Advanced Computer Architecture (2.0 - 2016 Edition**)
< from Pipelined CMOS Microprocessors to Multi/Mani-Cores, and Emerging Nanoscale Unconventional Architectures >
** Note: only limited basic architecture will be covered in 2016 - course will be different than in 2010-2015 **
Instructor: Csaba Andras-Moritz, Professor, Founder of BlueRISC and WindowsSCOPE
Research: research group (current focus on 3D IC nanofabrics and nanoscale architectures - CPU and unconventional)
Office: room KEB-20x
Instructor's web site: http://www.ecs.umass.edu/ece/andras
Admininstrative Assistant: Christine Langlois, phone: 413-545 3621
Office hours: Tue and Th11:30PM-12:30PM, or by email appointment
Office location: Knowles 2nd floor next to elevator
Class time: Tue-Th from 1PM-2:15PM
Class location: Marston 220 (double check Spire to confirm)
Class TA: Jiajun Shi (Jiajun Shi <email@example.com>), my PhD Student working on 3D Post-CMOS Tech and Processors
- Research papers and other materials are distributed in class or posted on this page. Please always refresh page so that you are not accessing a cached copy.
- We may get assigned another part-time TA depending on enrollment.
- Please check prerequisites before you take on the class.
- I recommend that you take ECE 568 and/or have strong background. In some cases strong motivation is fine too but this course will be hard w/o proper background
- What you must know: MIPS architecture, Pipelining, Pipeline Control, Datapath, Hazards, Hazard Management, Instruction Sets, Branch Prediction Schemes, Caches, Virtual Memory, TLB Design and Page Tables, Buses, Basic Out-of-Order/Tomasulo, Basic multi-core/ILP, Role of Compilers in Architecture, Basic VLSI
- Tools: you shall be able to write tools in C or C++ or Perl or other scripting language
- Some projects require HSPICE and CAD tools
- For access to slides and other class material/deadlines please see below on this page
Course Abstract: This course will cover advanced topics in computer architectures focusing on emerging uniprocessor and multiprocessor architectures, implementation issues (architect's perspective) in deep submicron CMOS, as well as nanoscale fabrics and architectures based on new types of emerging devices. Outline: (1) Introduction; (2) Pipelined Von Neumann Processors - Power Management Issues including Compiler-Exposed; (3) Power-Aware Branch Prediction and Control-Flow; (4) Process Variation Mitigation in Pipelines; (5) Process Variation Mitigation in Caches; (6) Hardware and Compiler-Managed Prefetching; (7) Power-Aware Prefetching with Compiler Assist; (8) Out-of-order Processors; (9) Superscalars, SMT, and VLIW CPUs; (10) Intel Multi-Cores and Emerging Many-Cores; (11) Shared Memory Multi-Processors, Cache Coherency Scheme (Snooping & Directory-based); (12) Transactional Memory; (13) Synchronization Coherence; (14) Interconnection Networks/IO; (15) 3D IC Technology and Emerging 3D Processors; (16) Unconventional (Non Von Neumann) Architectures (Probabilistic, Neuromorphic). (3 credits)
Projects/Exams/Grading: This is a *core* graduate-level course. Active student participation is expected. The course will have a project (to be selected), one midterm and a final exam. Projects will be listed below but other research-oriented projects can be pursued with instructor approval. Students can choose the project they prefer. Grading: 5% class participation, 30% Project 1 or Project 2, 35% midterm, 30% final exam, and 0% homeworks. Projects should be done in groups of up to three students (four only with approval).
Prerequisites: If you are taking this course you must have already taken an undergraduate-level architecture course (no exceptions) and have basic understanding of computer organization, VLSI, and microprocessor architecture (see below for what you are expected to know). The projects require good command of programming in either ASM, C, C++, C#, Java or Verilog. For Project 2-3, you need experience with HSPICE and VLSI.
- research papers - will be listed on this website or distributed
-  Hennesy and Patterson, Computer Architecture A Quantitative Approach, 4th or later Edition - this is the main textbok for embedded processors and superscalars
-  Parallel Computer Organization and Design, Michel Dubois, University of Southern CaliforniaMurali Annavaram, University of Southern CaliforniaPer Stenström, Chalmers University of Technology, Gothenberg, ISBN: 9780521886758 - this is main textbook for parallel processor part
-  J. P. Shen and Mikko H. Lipasti, Modern Processor Design
-  NASIC, N3ASIC, Skybridge 3D IC Nanofabrics post CMOS, and SPWF (spin wave) nanoarchitecture papers
-  NASIC textbook chapter - see link above
-  Rebooting Computing papers (IEEE Computer Magazine, December 2015 Special Issue) -please google
- Multiprocessor Synchronization Coherence Paper - see instructors papers list
- Transactional Memory Paper
- Raw Many-Core Processors /Tilera
- ARM CPUs in SoCs
- Monolythic 3D CMOS, Skybridge 3D Nanowire Architecture Papers
Other useful books to have:
-  Chandrakasan et al, Design of High-Performance Microprocessor Circuits
-  Jan M. Rabaey, Digital Integrated Circuit
- Descriptions for Project 1 (CMOS processor related) and Project 2 (NASIC processor related). Project 3 (3D Skybridge CMOS Processor Design)
- DUE May 4th, 2016, 1PM office in Knowles 309H. Details communicated in class.
- Project 1 help/instructions from the TA in 2008, Mid Project Review tbd, Final Project Review. gcc-2.7.2.
- Project 2 Help - N3ASIC device models. Also includes a readme file that explains how to use the device models, and an example of HSPICE netlist for a 2-input NAND gate.
- Project 3 - 3D Microprocessor Design - various ideas
- TA will coordinate model files needed for various projects
Jan 17, 2016
Copyright Csaba Andras Moritz 2008-2016