Department of Electrical and Computer Engineering                      University of Massachusetts Amherst

ECE 668 - Spring 2016 - Welcome 

Advanced Computer Architecture (2016 Edition**)

< from CMOS Microprocessors to Multi/Mani-Cores, and Emerging Nanoscale Unconventional Architectures >

** Note: only limited basic architecture will be covered in 2016 - course will be different than in 2010-2015 **

InstructorCsaba Andras-Moritz, Professor, Founder of BlueRISC and WindowsSCOPE
Research: research group (current focus on 3D IC nanofabrics and nanoscale architectures - CPU and unconventional)
Office: room KEB-20x

Instructor's web site:
Admininstrative Assistant:   Christine Langlois, phone: 413-545 3621
Office hours: Tue and Th11:30PM-12:30PM, or by email appointment
Office location: Knowles 2nd floor next to elevator
Class time: Tue-Th from 1PM-2:15PM
Class location:  Marston 220 (double check Spire to confirm)
Class TA
: Jiajun Shi (Jiajun Shi <>), PhD Student working on 3D Post-CMOS Tech and Processors


Course Abstract: This course will cover advanced topics in computer architectures focusing on emerging uniprocessor and multiprocessor architectures, implementation issues (architect's perspective) in deep submicron CMOS, as well as nanoscale fabrics and architectures based on new types of emerging devices. Outline: (1) Introduction; (2) Pipelined Von Neumann Processors - Power Management Issues including Compiler-Exposed; (3) Power-Aware Branch Prediction and Control-Flow; (4) Process Variation Mitigation in Pipelines; (5) Process Variation Mitigation in Caches; (6) Hardware and Compiler-Managed Prefetching; (7) Power-Aware Prefetching with Compiler Assist; (8) Out-of-order Processors; (9) Superscalars, SMT, and VLIW CPUs; (10) Intel Multi-Cores and Emerging Many-Cores; (11) Shared Memory Multi-Processors, Cache Coherency Scheme (Snooping & Directory-based); (12) Transactional Memory; (13) Synchronization Coherence; (14) Interconnection Networks/IO; (15) 3D IC Technology and Emerging 3D Processors; (16) Unconventional (Non Von Neumann) Architectures (Probabilistic, Neuromorphic).   (3 credits)

Projects/Exams/Grading: This is a *core* graduate-level course. Active student participation is expected.  The course will have a project (to be selected), one midterm and a final exam. Projects will be listed below but other research-oriented projects can be pursued with instructor approval. Students can choose the project they prefer. Grading: 5% class participation, 30% Project 1 or Project 2, 35% midterm, 30% final exam, and 0% homeworks.  Projects should be done in groups of up to three students (four only with approval).

Prerequisites: If you are taking this course you must have already taken an undergraduate-level architecture course (no exceptions) and have basic understanding of computer organization, VLSI, and microprocessor architecture (see above for what you are expected to know). The projects require good command of programming in either ASM, C, C++, C#, Java or Verilog. For Project 2-3, you need experience with HSPICE and VLSI.

Materials from:

Other useful books to have:

  • Midterm Exam: in regular classroom, 1 hour, after spring break (MARCH 29), 2016, Midterm Review
  • Final Exam: April 26, 2016, in regular classroom at 1PM, Final Review
  • Project demos: April 28 11-30-2PM in instructor's office, email the report and source before to instructor and TA

Last updated: April 2, 2016

Copyright Csaba Andras Moritz 2008-2016