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Csaba Andras Moritz 
andras@ecs.umass.edu
(413) 545-2442
 

Secretary:
Chris Langlois
Phone:
(413)-545-3621

Address:
University of Massachusetts, Amherst,
Elect. and Comp. Eng.
Knowles Eng. Building,
309H,  Amherst, MA 01003
Map

Figure: 2-bit NASIC ALU with silicon nanowires

I'm an associate professor in the Electrical and Computer Engineering department at the University of Massachusetts Amherst.  I am the nanoelectronics TRG research leader (with Prof Mark Tuominen, physics) at the CHM/NSEC nanoscience center and a PI in nano architectures at the FENA MARCO/SRC-sponsored research center. My students and I are the recent winners of the IEEE Symposium on VLSI 2008 Best Paper award and a Best Research Poster award (in the nanoscale architectures category) at the FENA/MARCO 2008 annual review. I am also affiliated with BlueRISC Inc, a startup company I have founded, focusing on end-point security microprocessors and hardware-assisted security solutions.   

RESEARCH: My group's current research focus is on developing fault-tolerant nanoscale circuits, nanoscale processor designs, and suitable fabric architectures based on emerging device and manufacturing paradigms. A key focus is on NASICs. This work is sponsored by  FENA/MARCO, NSF/NER, CHM and NSF/CCR awards.

My earlier research focused on  power-aware compiler-enabled computer architectures with occasional circuit-level work. This work was sponsored by an NSF/ITR award. Other research focused on fine-grained synchronization - sponsored by an NSF architecture award.  

FORMER GRAD STUDENTS: Some of my former students are key architects at Google, BlueRISC, Microsoft, etc. Yao Guo is an assistant professor at Beijing University. Osman Unsal (co-advised with Mani Krishna and Israel Koren) is a researcher at Universitat Politecnica de Catalunia  in Barcelona. Mahmoud Bennaser is  a professor at Kuwait University. 

SERVICE: I was an  associate editor of IEEE Transactions on Computers between 2001-2006. Currently, I am a member of the ACM/SIGDA technical committee on emerging technologies.  A list of recent service activities and recent invited talks are provided below.

TEACHING: OS (undergraduate), parallel computer architectures (graduate), software-exposed architectures (graduate), nanoelectronics (graduate), advanced computer architecture (graduate), and low power microprocessor design (graduate). I am  leading the nano-architecture research initiative at UMass. My lecture notes and more details about these classes can be accessed here.

OTHER BACKGROUND INFO: I have a mixed academic and industrial background.  I have  worked in industry  in different roles, e.g., as CEO/CTO, consultant, board member,  and founder.   I lived and worked in 5 countries and have been fortunate to be employed in 5 universities (although for very short times). Before joining UMASS I was a research scientist at MIT (1997-2000), Laboratory for Computer Science.  I have earned my PhD in computer systems from the Royal Institute of Technology (KTH), Stockholm, Sweden, and my MS in electronics in 1985.  I also worked for a short period at EPCC and University of Edinburgh in 1996.  My earlier research projects include:  Hot Pages, a compiler-enabled software caching system for Raw microprocessors (with Saman Amarasinghe et al),   SUDS , a compiler-enabled speculative-execution   system for Raw (collaboration with Matt Frank et al), LoGPC, a model for estimating network contention on multiprocessors (with Matt Frank), SimpleFit or analytical modeling of Raw architectures (with Donald Yeung and Anant Agarwal), MPI performance evaluation and modeling (on Cray T3D, Convex Exemplar, Meiko and network of workstations), silicon compilation (with Jonathan Babb, Martin Rinard, et al), and multiprocessor scheduling (with Lars Erik Thorelli).