[Random Info (Below) | Nanoscale Computing Fabrics/Architectures Laboratory| Recent Papers |Classes I Teach]
Figures – Below: 2-bit NASIC ALU with nanowires; Right column: nanofabric components – graphene, nanowire, spin based– AFM images sub 30nm
I'm an entrepreneur and professor in the Electrical and Computer Engineering department at the University of Massachusetts in Amherst. I am focusing on nanoscale computing fabrics, associated models of computation (often different than von Neumann) and electronics beyond CMOS. Nanofabrics initiated in my group include NASICs, Spin Wave Functions, N3ASICs, etc. My other technical interest is in (architecting for) security. I founded BlueRISC Inc in 2002, a company that develops anti-tamper security microprocessors and solutions. WindowsSCOPE, another of my recent initiatives, targets cyber security and forensics tools. I teach entrepreneurship and technical topics.
I am the Director of the Nanoscale Architectures Laboratory. I lead the Nanoelectronics Technical Research Group (with Prof Mark Tuominen, Physics) at the CHM/NSEC NSF-sponsored nanoscience center. I was the General Chair of Nanoarch IEEE/ACM International Symposium in 2011, 2012, 2013 and am Co-General Chair in 2014 (conference will be organized in Paris). I am an Associate Editor (AE) for IEEE Transactions on Nanotechnology and Guest Editor of the Elsevier JPDC Special Issue: Computing with Future Nanotechnology. I am also the Guest Editor of a Special Issue/Section on Neuromorphic/brain-like Computing with Nanotechnology in IEEE Transactions on Nanotechnology and a member of the ACM/SIGDA technical committee on emerging technologies. I served as an AE of IEEE Transactions on Computers between 2001-2006. I was the Theme Lead for the Nanofabrics research theme at the FENA/FCRP-DARPA nanoarchitectonics research center 2009-2012.
OPEN POSITIONS: PhD, MS, and postdoc.
RESEARCH: My group's current research focus is on post-CMOS nanoscale fabrics and associated models of computation, based on emerging device (nanowire, spintronics, and graphene, especially) and novel nanomanufacturing paradigms. We do experimental (Cleanroom) work in addition to cross-layer (device-circuit-fabric/architecture) theoretical explorations. We recently demonstrated experimentally N3ASIC nanofabric components and junctionless depletion-mode xnwFET cross-point devices at sub 30nm scale. My earlier projects also included low-power microprocessor design, fine grained synchronization in multiprocessors, single-chip multiprocessor architectures, compilers, etc.
RECENT AWARDS in my group: IEEE/ACM Symposium on Nanoscale Architectures Best Paper Award 2013, Best 20 Last 25 Years Paper Award at IEEE Symposium on Custom Computing Machines 2013, IEEE Symposium on VLSI 2008 Best Paper award (out of 220+ papers), Best Student Paper at IEEE DFT 2010, Best Student Paper Award at IEEE/ACM Symposium on Nanoscale Architectures 2011, Best Student Paper IEEE DFT 2011 and several Best Research Poster awards at the FENA/FCRP annual reviews including at MIT in 2011 and UCLA in 2012.
FORMER STUDENTS: Some of my former students are academics or leading architects at Google, Microsoft, Qualcomn, Marwell, IBM, Intel, Lattice, BlueRISC, Nvidia, Tensilica, etc. They work on both conventional and emerging nanoscale computing and associated technology development.
Some examples: Pritish Narayanan is a researcher at IBM Research in Almaden in nanoelectronics, Yao Guo is an associate professor at Peking University. Mahmoud Bennaser is an assistant professor at Kuwait University. Osman Unsal (co-advised) is a senior computer architecture researcher at Universitat Politecnica de Catalunia in Barcelona. Tom Wang works on nanoscale CMOS technology at Qualcomm. Raksit Ashok is a compiler architect at Google, Saurabh Chheda is a CPU architect at Tensilica.
TEACHING: entrepreneurship (undergrad/graduate), advanced computer architecture (graduate), nanoscale fabrics and architectures (graduate), computer systems lab I (undergrad), computer systems lab II (undergrad), OS (undergrad), parallel architectures (graduate), and low-power microprocessors (graduate).
PHD/POST-DOC ADVISORS: Lars-Erik Thorelli (Royal Institute of Technology, Stockholm), Anant Agarwal (MIT), Saman Amarasinghe (MIT)
Last updated on Dec 7, 2012