[Random Info (Below) | Nanoscale Computing Fabrics/Architectures Laboratory| Papers |Classes I Teach]
Figures – Below: 2-bit NASIC ALU with nanowires; Right column: nanofabric components – graphene, nanowire, spin based– AFM images sub 30nm
My research group is focusing on nanoscale computing fabrics and associated models of computation (often unconventional - different than von Neumann). Our current direction is on 3D nanofabrics for cognitive and microprocessor ICs (Skybridge, 3D Fine-Grained CMOS) and on Causal Intelligence Architectures with nanotechnology. Our Bayesian approach one of the 5 papers selected for Rebooting Computing Special Issue in IEEE Computer (Dec, 2015). Other nanofabrics initiated in my group include NASICs, Spin Wave Functions, N3ASIC, Bayesian magneto-electric directions, wave interference computing with spin devices, etc. We do occasional experimental (Cleanroom) work in addition to detailed cross-layer (device-circuit-architecture) theoretical explorations. We demonstrated experimentally the N3ASIC nanofabric at sub-30nm scale in 2014 and working on 3D Skybridge. I teach entrepreneurship and technical topics. My group is a winner of 9 Best Paper/Poster awards since 2008.
My other interest is in architecting for security and is related to my entrepreurial activities. I founded BlueRISC Inc in 2002, a technology company that develops softcore security microprocessors and system assurance tools & solutions, including for software vulnerability analysis. WindowsSCOPE, another of my initiatives, targets cyber-security forensics tools. These systems and tools are sold in 16 countries.
I am the Director of the Nanoscale Architectures Laboratory. I co-lead the Nanoelectronics Technical Research Group at the CHM/NSEC NSF-sponsored nanoscience center and am also a member of its executive committee. I was a member of the FENA/FCRP-DARPA nanoarchitectonics research center executive committee and a Theme Lead for the Nanofabrics research theme between 2008-2012.
I am the General Chair of of Nanoarch IEEE/ACM International Symposium on Nanoscale Architectures in 2017 in Newport, RI. I was General Chair or Co-Chair in 2011, 2012, 2013, 2014, 2015, 2016 (San Diego, Amsterdam, NYC, Paris, Boston, and Bejing).
I was the first steering commitee chair of IEEE Transactions on Multi-Scale Systems (helped with its launch and editorial board, 2014-2015), was an Associate Editor (AE) for IEEE Transactions on Nanotechnology (2009-2015). I served as an AE of IEEE Transactions on Computers (2001-2006). I was the Guest Editor of the Elsevier JPDC Special Issue: Computing with Future Nanotechnology. I am currently the Guest Editor of a Special Issue on 3D ICs (2016, Revolutionary 3-D Integration and Design for Next Generation Computing), and Computing with Nanotechnology (in IEEE Transactions on Nanotechnology). I am a member of the ACM/SIGDA technical committee on emerging technologies.
OPEN POSITIONS: PhD, MS, and postdoc.
RESEARCH: My group's research focus the last ten years is on post-CMOS nanoscale fabrics and associated models of computation. My earlier projects also included low-power microprocessor design, fine grained synchronization in multiprocessors, single-chip multiprocessor architectures, parallelizing compilers, etc.
SOME AWARDS in my group: IEEE/ACM Symposium on Nanoscale Architectures Best Paper Award 2013 & 2014, Best 20 Last 25 Years Paper Award at IEEE Symposium on Custom Computing Machines 2013, IEEE Symposium on VLSI 2008 Best Paper award (out of 220+ papers), Best Student Paper at IEEE DFT 2010, Best Student Paper Award at IEEE/ACM Symposium on Nanoscale Architectures 2011, Best Student Paper IEEE DFT 2011 and several Best Research Poster awards at the FENA/FCRP annual reviews including at MIT in 2011 and UCLA in 2012.
FORMER STUDENTS: Some of my former grad students work in academia (4) or are leading architects at Google, Microsoft, Qualcomn, Marwell, IBM, Intel, Lattice, BlueRISC, Nvidia, Tensilica, etc. They work on both conventional and emerging nanoscale computing and associated technology development.
Examples: Rahman Mostafizur is a professor at the Univ of Missouri; Pritish Narayanan is a researcher at IBM Research in Almaden, Ca; Yao Guo is an associate professor at Peking University. Mahmoud Bennaser is a professor at Kuwait University. Osman Unsal (co-advised) is a senior computer architecture researcher at Universitat Politecnica de Catalunia in Barcelona. Santosh Khasanvis is a senior research scrientist at BlueRISC. Tom Wang works on nanoscale CMOS technology at Qualcomm. Raksit Ashok is a compiler architect at Google, Saurabh Chheda is a CPU architect at Tensilica. Prasad Shabadi is a CPU architect at Intel.
TEACHING: entrepreneurship, advanced computer architecture (graduate), nanoscale fabrics and architectures (graduate), computer systems lab I (undergrad), computer systems lab II (undergrad). Also taught OS (undergrad), parallel architectures (graduate), and low-power microprocessors (graduate).
PHD / POST-DOC ADVISORS: Lars-Erik Thorelli (Royal Institute of Technology, Stockholm) / Anant Agarwal (MIT), Saman Amarasinghe (MIT)
Last updated on Sept 17, 2016