[Projects]

[Classes]

[Publications ]  

Csaba Andras Moritz 

andras@ecs.umass.edu
(413) 545-2442 

Administrative Assistant:
Christine Langlois
Phone:
(413)-545-3621

Address:
University of Massachusetts, Amherst,
Elect. and Comp. Eng.
Knowles Eng. Building,
309H,  Amherst, MA 01003
Map

Figure: 2-bit NASIC ALU with silicon nanowires

I'm a professor in the Electrical and Computer Engineering department at the University of Massachusetts in Amherst where I am focusing on nanoscale computing fabrics and electronics.  Nanofabrics initiated in my group include NASICs, Spin Wave Functions, N3ASICs, and N3P.

I am also affiliated with BlueRISC Inc, a company I founded in 2002, that develops and sells end-point/anti-tamper security processors and hardware-assisted solutions for anti tamper (TrustGUARD products). WindowsSCOPE targets cyber security and memory forensics.

I was the General Chair of Nanoarch '11 the IEEE/ACM International Symposium on Nanoscale Architectures.  I lead the Nanoelectronics Technical Research Group (with Prof Mark Tuominen, Physics) at the CHM/NSEC NSF-sponsored nanoscience center. I am also the Theme Lead for the Nanofabrics research theme at the FENA/FCRP nanoarchitectonics research center, funded by SRC and DARPA, and involved in the DARPA NVL project. Further, I am the Director of the Nanoscale Architectures Laboratory. Some of my other affiliations include being an Associate Editor of IEEE Transactions on Nanotechnology.

OPEN POSITIONS: PhD, MS, and postdoc positions. Preference currently are candidates with circuits/VLSI, architecture, nanoscale device and nanomanufacturing expertise.

RESEARCH: My group's current research focus is on nanoscale computational fabrics and associated models of computation. We are developing fault-tolerant nanoscale circuits, nanoscale processors, neuromorphic systems, suitable fabric architectures and logic based on emerging device and manufacturing paradigms. Our approach is based on an integrated exploration considering physical layer aspects carefully, including nanomanufacturing and device-fabric interactions. These projects are sponsored by  FENA, CHM, DARPA and NSF awards.

RECENT AWARDS : Finalists for the IEEE/ACM International Symposium on Nanoscale Architectures 2009 Best Paper Award, winners of the IEEE Symposium on VLSI 2008 Best Paper award (out of 220+ papers), Best Student Paper at IEEE DFT 2010, Best Student Paper Award at IEEE/ACM Nanoarch 2011, and Best Research Poster awards (in the nanoscale architectures category) at the FENA/MARCO 2008 and 2011 annual reviews.

My earlier research focused on  power-aware compiler-enabled computer architectures and some related circuit-level work. Sponsored by an NSF/ITR award. Other research focused on fine-grained synchronization - sponsored by an NSF architecture award. My other interest is in security (see BlueRISC).  

FORMER STUDENTS: Some of my former students are academics or key architects at Google, Microsoft, Qualcomn, Intel, Lattice, BlueRISC, WindowsSCOPE, etc. Yao Guo is an associate professor at Beijing University. Mahmoud Bennaser is  an assistant professor at Kuwait University. Osman Unsal (co-advised with Mani Krishna and Israel Koren) is a researcher at Universitat Politecnica de Catalunia  in Barcelona. Tom Wang works on some cool stuff at Qualcomm. Raksit Ashok is a leading compiler guy at Google...

EDITORIAL: I am an Associate Editor (AE) for IEEE Transactions on Nanotechnology. I served as an AE of IEEE Transactions on Computers between 2001-2006. I am also a member of the ACM/SIGDA technical committee on emerging technologies.  A list of other recent service activities is provided below.

TEACHING: advanced computer architecture (graduate), computer systems lab I (undergraduate), computer systems lab II (undergraduate), OS (undergraduate), parallel computer architectures (graduate), software-exposed architectures (graduate), nanoelectronics and nanoscale architectures (graduate), and low power microprocessor design (graduate).

OTHER EXPERIENCE: I have a mixed academic and industrial background.  I have  worked in industry  in different roles, e.g., as CEO/CTO, consultant, board member,  and founder.   I lived and worked in 5 countries and have been fortunate to be employed in 5 universities (although some for very short times). Before joining UMASS I was a research scientist at MIT (1997-2000), Laboratory for Computer Science; these years were critical to my formation as a researcher. I have earned my PhD in computer systems from the Royal Institute of Technology (KTH), Stockholm, Sweden, and my MS in electronics in 1985.  I also worked for a short period at EPCC and University of Edinburgh in 1996.  My earlier research projects include:  Hot Pages, a compiler-enabled software caching system for Raw microprocessors (with Saman Amarasinghe, Anant Agarwal, et al),   SUDS , a compiler-enabled speculative-execution   system for Raw (collaboration with Matt Frank and others), LoGPC, a model for estimating network contention on multiprocessors (with Matt Frank), SimpleFit or analytical modeling of Raw architectures (with Donald Yeung and Anant Agarwal), MPI performance evaluation and modeling (on Cray T3D, Convex Exemplar, Meiko and network of workstations), silicon compilation (with Jonathan Babb, Martin Rinard, et al), and multiprocessor scheduling (with Lars Erik Thorelli, my advisor at KTH).