Reconfigurable FPGA Co-Processors for Wireless Data Communications

Apurva Brahmbhatt and Wayne Burleson
University of Massachusetts at Amherst

Abstract

We explore the use of Field Programmable Gate Arrays as a hardware platform for reconfigurable co-processors to support compute-intensive functions in wireless data communications. Wireless networks present a unique combination of complex and time-varying computational requirements along with tight constraints on cost, physical size and power consumption. Reconfigurable component technology in the form of Field Programmable Gate Arrays (FPGAs) has emerged in the last several years, however existing CAD tools and design methods are not well-suited for the algorithms and architectures which arise in data communications. Also, rather than just conventional FPGAs, combinations of FPGA technology with existing processor cores and memories will be more appropriate for this type of computations. Therefore new design methods and tools addressing this type of hybrid architecture must be developed.

In this paper, we describe initial results related to this large research problem. We have developed a prototype which uses Altera Flex10K FPGAs to swap between high-performance implementations of Lempel-Ziv data compression and RSA cryptography. Both algorithms are implemented as parameterized designs. The swapping between the two algorithms is orchestrated by a PIC microcontroller and externals. We will present performance and power estimates of this prototype as well as future plans to generalize to other communications algorithms and scaling of the entire design onto a single integrated circuit.

Apurva Brahmbhatt
Department of ECE
University of Massachusetts at Amherst
Tel: (413)-545-2382
Fax: (413)-545-1993
abrahmbh@ecs.umass.edu

Wayne Burleson
Department of ECE
University of Massachusetts at Amherst
Tel: (413)-545-2382
Fax: (413)-545-1993
burleson@ecs.umass.edu